10 Commits

Author SHA1 Message Date
Nicola Zaghen 0818e789cb Rename DEBUG macro to LLVM_DEBUG.
The DEBUG() macro is very generic so it might clash with other projects.
The renaming was done as follows:
- git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g'
- git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
- Manual change to APInt
- Manually chage DOCS as regex doesn't match it.

In the transition period the DEBUG() macro is still present and aliased
to the LLVM_DEBUG() one.

Differential Revision: https://reviews.llvm.org/D43624



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332240 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-14 12:53:11 +00:00
Shiva Chen bcdec40008 [RISCV] Implement c.lui immediate operand constraint
Implement c.lui immediate constraint to [1, 31] and [0xfffe0, 0xfffff].
The RISC-V ISA describes the constraint as [1, 63], with that value
being loaded in to bits 17-12 of the destination register and sign extended
from bit 17. Therefore, this 6-bit immediate can represent values in the
ranges [1, 31] and [0xfffe0, 0xfffff].

Differential Revision: https://reviews.llvm.org/D42834

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325792 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-22 15:02:28 +00:00
Alex Bradbury 6d0dcae300 [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention
When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.

This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.

Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320560 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 09:57:25 +00:00
Alex Bradbury 5774b87aa7 [RISCV] MC layer support for the remaining RVC instructions
Differential Revision: https://reviews.llvm.org/D40003

Patch by Shiva Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320558 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 09:32:55 +00:00
Alex Bradbury a73fa87189 [RISCV] MC layer support for load/store instructions of the C (compressed) extension
Differential Revision: https://reviews.llvm.org/D40001
    
Patch by Shiva Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320037 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-07 12:50:32 +00:00
Alex Bradbury 42a025965e [RISCV] MC layer support for the standard RV32D instruction set extension
As the FPR32 and FPR64 registers have the same names, use 
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an 
FPR64 when necessary. The rest of this patch is very similar to the RV32F 
patch.

Differential Revision: https://reviews.llvm.org/D39895


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320023 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-07 10:46:23 +00:00
Alex Bradbury e65af32d44 [RISCV] MC layer support for the standard RV32F instruction set extension
The most interesting part of this patch is probably the handling of 
rounding mode arguments. Sadly, the RISC-V assembler handles floating point 
rounding modes as a special "argument" when it would be more consistent to 
handle them like the atomics, opcode suffixes. This patch supports parsing 
this optional parameter, using InstAlias to allow parsing these floating point 
instructions when no rounding mode is specified.

Differential Revision: https://reviews.llvm.org/D39893


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320020 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-07 10:26:05 +00:00
Alex Bradbury d0f69295c9 [RISCV][NFC] Remove unnecessary {} around single statement if block
Almost too trivial to worry about, but it seems worth having consistency with
upcoming commits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318760 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-21 12:41:41 +00:00
Alex Bradbury 1437cc9a52 [RISCV] Prepare for the use of variable-sized register classes
While parameterising by XLen, also take the opportunity to clean up the 
formatting of the RISCV .td files.

This commit unifies the in-tree code with my patchset at 
<https://github.com/lowrisc/riscv-llvm>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316159 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-19 14:29:03 +00:00
Alex Bradbury a1c2bb91ad [RISCV] Add support for disassembly
This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s
has been updated appropriately.

Differential Revision: https://reviews.llvm.org/D23567


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313486 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-17 14:36:28 +00:00