3 Commits

Author	SHA1	Message	Date
Alex Bradbury	dcfcbe7bdc	[RISCV] Implement prolog and epilog insertion ... As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320357 91177308-0d34-0410-b5e6-96231b3b80d8	2017-12-11 12:34:11 +00:00
Alex Bradbury	1e4e4646ad	[RISCV] Support lowering FrameIndex ... Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320353 91177308-0d34-0410-b5e6-96231b3b80d8	2017-12-11 11:53:54 +00:00
Alex Bradbury	5a3d179fab	[RISCV] Initial codegen support for ALU operations ... This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316188 91177308-0d34-0410-b5e6-96231b3b80d8	2017-10-19 21:37:38 +00:00