3 Commits

Author SHA1 Message Date
Oren Ben Simhon
c934c63c3a [X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
Fixing build issues.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290244 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 08:59:42 +00:00
Oren Ben Simhon
7327d6f7aa [X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
The vectorcall calling convention specifies that arguments to functions are to be passed in registers, when possible.
vectorcall uses more registers for arguments than fastcall or the default x64 calling convention use. 
The vectorcall calling convention is only supported in native code on x86 and x64 processors that include Streaming SIMD Extensions 2 (SSE2) and above.

The current implementation does not handle Homogeneous Vector Aggregates (HVAs) correctly and this review attempts to fix it.
This aubmit also includes additional lit tests to cover better HVAs corner cases.

Differential Revision: https://reviews.llvm.org/D27392



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290240 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 08:31:45 +00:00
Oren Ben Simhon
92dbb1780d [X86] RegCall - Handling v64i1 in 32/64 bit target
Register Calling Convention defines a new behavior for v64i1 types.
This type should be saved in GPR.
However for 32 bit machine we need to split the value into 2 GPRs (because each is 32 bit).

Differential Revision: https://reviews.llvm.org/D26181

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287217 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-17 09:59:40 +00:00