Commit Graph

7706 Commits

Author SHA1 Message Date
Pawel Bylica fadb1c1c61 Merging r286998:
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r286998 | chfast | 2016-11-15 19:29:24 +0100 (wto, 15 lis 2016) | 12 lines

Integer legalization: fix MUL expansion

Summary:
This fixes the runtime results produces by the fallback multiplication expansion introduced in r270720.

For tests I created a fuzz tester that compares the results with Boost.Multiprecision.

Reviewers: hfinkel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26628


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@288086 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-28 22:45:01 +00:00
Pawel Bylica 9b2f9c4eed Merging r281403:
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r281403 | chfast | 2016-09-13 23:55:41 +0200 (wto, 13 wrz 2016) | 9 lines

[CodeGen] Fix invalid shift in mul expansion

Summary: When expanding mul in type legalization make sure the type for
shift amount can actually fit the value.
This fixes PR30354 https://llvm.org/bugs/show_bug.cgi?id=30354.

Reviewers: hfinkel, majnemer, RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: https://reviews.llvm.org/D24478


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@288085 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-28 22:41:59 +00:00
Hans Wennborg f89a462dfb Merging r277371:
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r277371 | mkuper | 2016-08-01 12:39:49 -0700 (Mon, 01 Aug 2016) | 9 lines

[DAGCombine] Make sext(setcc) combine respect getBooleanContents

We used to combine "sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)"
Instead, we should combine to (select (setcc x, y, cc), T, 0) where the value
of T is 1 or -1, depending on the type of the setcc, and getBooleanContents()
for the type if it is not i1.

This fixes PR28504.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@277509 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:54:53 +00:00
Hans Wennborg 4105790f15 Merging r277135:
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r277135 | niravd | 2016-07-29 04:49:32 -0700 (Fri, 29 Jul 2016) | 12 lines

Cleanup TransferDbgValues

[DAG] Check debug values for invalidation before transferring and mark
old debug values invalid when transferring to another SDValue.

This fixes PR28613.

Reviewers: jyknight, hans, dblaikie, echristo

Subscribers: yaron.keren, ismail, llvm-commits

Differential Revision: https://reviews.llvm.org/D22858
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@277164 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-29 16:18:18 +00:00
Chih-Hung Hsieh f94271deae [X86] Accept SELECT op code for x86-64 fp128 type
DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow
SELECT op code for x86_64 fp128 type for MME targets,
so SoftenFloatOperand does not abort on SELECT op code.

Differential Revision: http://reviews.llvm.org/D21758


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275818 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 17:20:09 +00:00
Simon Dardis 5ebefb8fd2 [inlineasm] Propagate operand constraints to the backend
When SelectionDAGISel transforms a node representing an inline asm
block, memory constraint information is not preserved. This can cause
constraints to be broken when a memory offset is of the form:

offset + frame index

when the frame is resolved.

By propagating the constraints all the way to the backend, targets can
enforce memory operands of inline assembly to conform to their constraints.

For MIPSR6, some instructions had their offsets reduced to 9 bits from
16 bits such as ll/sc. This becomes problematic when using inline assembly
to perform atomic operations, as an offset can generated that is too big to
encode in the instruction.

Reviewers: dsanders, vkalintris

Differential Review: https://reviews.llvm.org/D21615


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275786 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 13:17:31 +00:00
Justin Lebar b2d6ad7cfd [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends.
Summary:
Instead, we take a single flags arg (a bitset).

Also add a default 0 alignment, and change the order of arguments so the
alignment comes before the flags.

This greatly simplifies many callsites, and fixes a bug in
AMDGPUISelLowering, wherein the order of the args to getLoad was
inverted.  It also greatly simplifies the process of adding another flag
to getLoad.

Reviewers: chandlerc, tstellarAMD

Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits

Differential Revision: http://reviews.llvm.org/D22249

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275592 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 18:27:10 +00:00
Justin Lebar 14fc45e102 [CodeGen] Take a MachineMemOperand::Flags in MachineFunction::getMachineMemOperand.
Summary:
Previously we took an unsigned.

Hooray for type-safety.

Reviewers: chandlerc

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D22282

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275591 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 18:26:59 +00:00
Michael Kuperstein 95c81ed0a1 Fix copy/paste bug in r275340.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275343 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-13 23:28:00 +00:00
Michael Kuperstein a38e7e4c53 [DAG] Correctly chain masked loads
If a masked loads is not added to the chain, it should not reset the chain's
root.

This fixes the remaining part of PR28515.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275340 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-13 23:23:40 +00:00
Andrew Kaylor b9ed6a643a Reverting r275284 due to platform-specific test failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275304 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-13 19:09:16 +00:00
Andrew Kaylor c949e6e642 Fix for Bug 26903, adds support to inline __builtin_mempcpy
Patch by Sunita Marathe

Differential Revision: http://reviews.llvm.org/D21920



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275284 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-13 17:25:11 +00:00
Sanjay Patel 7228de8778 fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275101 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-11 20:50:39 +00:00
Sanjay Patel 03c714d84a [DAG] make isConstantSplatVector() available to the rest of lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275025 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-10 21:27:06 +00:00
Sanjay Patel 2495a35fca fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275021 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-10 21:02:16 +00:00
Sanjay Patel 7ea0bdecfe reformat, fix comments/names; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275015 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-10 13:05:57 +00:00
Benjamin Kramer a27e16e477 Give helper classes/functions internal linkage. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275014 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-10 11:28:51 +00:00
Sanjay Patel ed029b06bb fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274981 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-09 18:52:07 +00:00
Matt Arsenault db12f54967 Reapply r274829 with fix for FP vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274937 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 21:25:33 +00:00
Nico Weber b2e9a53e5c Revert r274829, it caused PR28472.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274916 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 19:52:19 +00:00
Duncan P. N. Exon Smith 86a3f7842e SelectionDAG: Avoid implicit iterator conversions in SelectionDAGBuilder, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274907 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 19:23:12 +00:00
Duncan P. N. Exon Smith 9ea0ae7891 SelectionDAG: Avoid implicit iterator conversions in SelectionDAGISel, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274904 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 19:11:40 +00:00
Duncan P. N. Exon Smith a60f808fc9 SelectionDAG: Avoid implicit iterator conversions in ScheduleDAGSDNodes, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274903 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 19:07:09 +00:00
Duncan P. N. Exon Smith cc2c87f587 SelectionDAG: Avoid implicit iterator conversions in FastISel, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274899 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 18:36:41 +00:00
Sjoerd Meijer d83fc587ba Do not expand SDIV when compiling for minimum code size
Differential Revision: http://reviews.llvm.org/D22139


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274855 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 15:32:01 +00:00
Sjoerd Meijer 234942365d Addressing post-commit comments regarding not expanding UDIV;
we don't expand only when compiling for minimum code size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274847 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 14:17:09 +00:00
Sjoerd Meijer c1abfa12f7 Code size optimisation: don't expand a div to a mul and and a shift sequence.
As a result, the urem instruction will not be expanded to a sequence of umull,
lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod.

Differential Revision: http://reviews.llvm.org/D22131


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274843 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 12:54:43 +00:00
Matt Arsenault 3e6afe96bf Bug 28444: Fix assertion when extract_vector_elt has mismatched type
For some reason extract_vector_elt is sometimes allowed to have
a different result type than the vector element type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274829 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 07:05:00 +00:00
Andrew Kaylor 9e4419db36 Include SelectionDAGISel in the opt-bisect process
Differential Revision: http://reviews.llvm.org/D21143



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274786 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-07 18:55:02 +00:00
Tim Shen 0cb64ba25c [DAGCombiner] Fix visitSTORE to continue processing current SDNode, if findBetterNeighborChains doesn't actually CombineTo it.
Summary:
findBetterNeighborChains may or may not find a better chain for each node it finds, which include the node ("St") that visitSTORE is currently processing. If no better chain is found for St, visitSTORE should continue instead of return SDValue(St, 0), as if it's CombinedTo'ed.

This fixes bug 28130. There might be other ways to make the test pass (see D21409). I think both of the patches are fixing actual bugs revealed by the same testcase.

Reviewers: echristo, wschmidt, hfinkel, kbarton, amehsan, arsenm, nemanjai, bogner

Subscribers: mehdi_amini, nemanjai, llvm-commits

Differential Revision: http://reviews.llvm.org/D21692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274644 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-06 17:44:03 +00:00
Balaram Makam 2973862bd9 Revert r259387: "AArch64: Implement missed conditional compare sequences."
This reverts commit r259387 because it inserts illegal code after legalization
    in some backends where i64 OR type is illegal for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274573 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-05 20:24:05 +00:00
Matt Arsenault 18a21c4966 DAGCombiner: Fold away vector extract of insert with the same index
This only really matters when the index is non-constant since the
constant case already gets taken care of by other combines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274569 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-05 18:25:02 +00:00
Craig Topper 061feda889 [CodeGen] Make the code that detects a if a shuffle is really a concatenation of the inputs more general purpose.
We can now handle concatenation of each source multiple times. The previous code just checked for each source to appear once in either order.

This also now handles an entire source vector sized piece having undef indices correctly. We now concat with UNDEF instead of using one of the sources. This is responsible for the test case change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274483 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-04 06:19:35 +00:00
Craig Topper 4eca4cb556 [CodeGen] Teach OR combine of shuffles involving zero vectors to better handle undef indices.
Undef indices can now be treated as zeros. Or if its undef ORed with zero, we will keep the undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274472 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-03 19:37:12 +00:00
Craig Topper bc6530574d [CodeGen] Cleanup getVectorShuffle a bit to take advantage of its new ArrayRef argument and its begin/end iterators. Also use 'int' type for number of elements and loop iterators to remove several typecasts. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274338 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-01 06:54:51 +00:00
Craig Topper a8fbaf1221 [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended.
For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274337 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-01 06:54:47 +00:00
Duncan P. N. Exon Smith a204da23db CodeGen: Use MachineInstr& in TargetLowering, NFC
This is a mechanical change to make TargetLowering API take MachineInstr&
(instead of MachineInstr*), since the argument is expected to be a valid
MachineInstr.  In one case, changed a parameter from MachineInstr* to
MachineBasicBlock::iterator, since it was used as an insertion point.

As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274287 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-30 22:52:52 +00:00
Rafael Espindola 809018e56e Delete unused includes. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274225 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-30 12:19:16 +00:00
Craig Topper 7268ea5189 [DAGCombine] Teach DAG combine to handle ORs of shuffles involving zero vectors where the zero vector is the first operand to the shuffle instead of the second.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274097 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-29 03:29:12 +00:00
Craig Topper 4cd293caf8 [CodeGen] Make ShuffleVectorSDNode::commuteMask take a MutableArrayRef instead of SmallVectorImpl. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274095 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-29 03:29:06 +00:00
Rafael Espindola c4cbe67fa8 Use isPositionIndependent in a few more places.
I think this converts all the simple cases that really just care about
the generated code being position independent or not. The remaining
uses are a bit more complicated and are checking things like "is this
a library or executable" or "can this symbol be preempted".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274055 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-28 20:13:36 +00:00
Rafael Espindola d980ed0d00 Move shouldAssumeDSOLocal to Target.
Should fix the shared library build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273958 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27 23:15:57 +00:00
Matt Arsenault bd288e1778 DAGCombiner: Don't narrow volatile vector loads + extract
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273909 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27 19:31:04 +00:00
Rafael Espindola a0e42848da Use isPositionIndependent predicate. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273830 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-26 22:38:44 +00:00
Rafael Espindola 678eac4d05 Use isPositionIndependent predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273828 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-26 22:30:06 +00:00
Rafael Espindola 73b2bb0c65 Refactor a duplicated predicate. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273826 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-26 22:13:55 +00:00
Craig Topper 63e75c45f1 [SelectionDAG] Use DAG.getCommutedVectorShuffle instead of reimplementing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273802 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-26 05:10:49 +00:00
Rafael Espindola fddccef6cb Use shouldAssumeDSOLocal in isOffsetFoldingLegal.
This makes it slightly more powerful for dynamic-no-pic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273704 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-24 18:48:36 +00:00
Nirav Dave 218e5843a6 Preserve DebugInfo when replacing values in DAGCombiner
Recommiting after correcting over-eager Debug Value transfer fixing PR28270.

[DAG] Previously debug values would transfer debuginfo for the selected
start node for a replacement which allows for debug to be dropped.

Push debug value transfer to occur with node/value replacement in
SelectionDAG, remove now extraneous transfers of debug values.

This refixes PR9817 which was being incompletely checked in the
testsuite.

Reviewers: jyknight

Subscribers: dblaikie, llvm-commits

Differential Revision: http://reviews.llvm.org/D21037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273585 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-23 17:52:57 +00:00
Peter Collingbourne 7cbcee7cad Revert r273456, "Preserve DebugInfo when replacing values in DAGCombiner" as it caused pr28270.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273518 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-23 00:06:17 +00:00