147 Commits

Author SHA1 Message Date
Sanjoy Das b166e6723e (Re-landing) Expose a TargetMachine::getTargetTransformInfo function
Re-land r321234.  It had to be reverted because it broke the shared
library build.  The shared library build broke because there was a
missing LLVMBuild dependency from lib/Passes (which calls
TargetMachine::getTargetIRAnalysis) to lib/Target.  As far as I can
tell, this problem was always there but was somehow masked
before (perhaps because TargetMachine::getTargetIRAnalysis was a
virtual function).

Original commit message:

This makes the TargetMachine interface a bit simpler.  We still need
the std::function in TargetIRAnalysis to avoid having to add a
dependency from Analysis to Target.

See discussion:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html

I avoided adding all of the backend owners to this review since the
change is simple, but let me know if you feel differently about this.

Reviewers: echristo, MatzeB, hfinkel

Reviewed By: hfinkel

Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D41464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321375 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22 18:21:59 +00:00
Sanjoy Das 0a1aae823b Revert "Expose a TargetMachine::getTargetTransformInfo function"
This reverts commit r321234.  It breaks the -DBUILD_SHARED_LIBS=ON build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321243 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21 02:34:39 +00:00
Sanjoy Das 0950f32a89 Expose a TargetMachine::getTargetTransformInfo function
Summary:
This makes the TargetMachine interface a bit simpler.  We still need
the std::function in TargetIRAnalysis to avoid having to add a
dependency from Analysis to Target.

See discussion:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html

I avoided adding all of the backend owners to this review since the
change is simple, but let me know if you feel differently about this.

Reviewers: echristo, MatzeB, hfinkel

Reviewed By: hfinkel

Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D41464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321234 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21 01:06:58 +00:00
Krzysztof Parzyszek 50b5493cd6 [Hexagon] Add support for Hexagon V65
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320404 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-11 18:57:54 +00:00
Krzysztof Parzyszek 4d7518052e [Hexagon] Allow the RDF optimizations to be run in .mir testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316904 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-30 14:11:52 +00:00
Krzysztof Parzyszek b99a8bcc2b [Hexagon] Allow redefinition with immediates for hw loop conversion
Normally, if the registers holding the induction variable's bounds
are redefined inside of the loop's body, the loop cannot be converted
to a hardware loop. However, if the redefining instruction is actually
loading an immediate value into the register, this conversion is both
possible and legal (since the immediate itself will be used in the
loop setup in the preheader).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316218 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20 16:56:33 +00:00
Krzysztof Parzyszek 59d5964ec6 [Hexagon] Minimize number of repeated constant extenders
Each constant extender requires an extra instruction, which adds to the
code size and also reduces the number of available slots in an instruction
packet. In most cases, the value of a repeated constant extender could be
loaded into a register, and the instructions using the extender could be
replaced with their counterparts that use that register instead.

This patch adds a pass that tries to reduce the number of constant
extenders, including extenders which differ only in an immediate offset
known at compile time, e.g. @global and @global+12.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315735 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-13 19:02:59 +00:00
Matthias Braun 9385cf15d1 Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"
Reverting to investigate layering effects of MCJIT not linking
libCodeGen but using TargetMachine::getNameWithPrefix() breaking the
lldb bots.

This reverts commit r315633.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315637 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-12 22:57:28 +00:00
Matthias Braun a063107f8d TargetMachine: Merge TargetMachine and LLVMTargetMachine
Merge LLVMTargetMachine into TargetMachine.

- There is no in-tree target anymore that just implements TargetMachine
  but not LLVMTargetMachine.
- It should still be possible to stub out all the various functions in
  case a target does not want to use lib/CodeGen
- This simplifies the code and avoids methods ending up in the wrong
  interface.

Differential Revision: https://reviews.llvm.org/D38489

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315633 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-12 22:28:54 +00:00
Pranav Bhandarkar 3e7d32b3f1 Enable the reuse of values computed in a previous loop iteration.
This patch adds a pass that removes the computation of provably redundant
expressions that have been computed earlier in a previous iteration. It
relies on the use of PHIs to identify loop carried dependences.

This is scalar replacement for vector types.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313925 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-21 21:48:23 +00:00
Krzysztof Parzyszek 0c3d5af968 [Hexagon] Add option to generate calls to "abort" for "unreachable"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312644 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-06 16:22:55 +00:00
Krzysztof Parzyszek 30898f12ad [Hexagon] Break up DAG mutations into separate classes, move to subtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311895 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-28 16:24:22 +00:00
Krzysztof Parzyszek 891663db21 [Hexagon] Move pre-RA DAG mutations to scheduler constructor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311894 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-28 15:52:54 +00:00
Krzysztof Parzyszek 5c985bdbe2 [Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-if
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310524 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-09 21:22:05 +00:00
Rafael Espindola 9aafb854cc Delete Default and JITDefault code models
IMHO it is an antipattern to have a enum value that is Default.

At any given piece of code it is not clear if we have to handle
Default or if has already been mapped to a concrete value. In this
case in particular, only the target can do the mapping and it is nice
to make sure it is always done.

This deletes the two default enum values of CodeModel and uses an
explicit Optional<CodeModel> when it is possible that it is
unspecified.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309911 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-03 02:16:21 +00:00
Krzysztof Parzyszek 33287d8a69 [Hexagon] Fix check for HMOTF_ConstExtend operand flag
This fixes https://llvm.org/PR33718.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307566 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 18:38:52 +00:00
Krzysztof Parzyszek ecf693d535 [Hexagon] Update kills in hexagon-nvj even more properly than before
Account for the fact that both, the feeder and the compare can be moved
over instructions that kill registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306443 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 18:37:16 +00:00
Krzysztof Parzyszek 5c1e1168dc [Hexagon] Remove call to printAndVerify from HexagonPassConfig
It causes an extra pass of the machine verifier to be added to the pass
manager, and causes test/CodeGen/Generic/llc-start-stop.ll to fail.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306140 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-23 18:47:55 +00:00
Krzysztof Parzyszek f65ef609fe [Hexagon] Don't kill live registers when creating mux out of tfr
When a mux instruction is created from a pair of complementary conditional
transfers, it can be placed at the location of either the earlier or the
later of the transfers. Since it will use the operands of the original
transfers, putting it in the earlier location may hoist a kill of a source
register that was originally further down. Make sure the kill flag is
removed if the register is still used afterwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305300 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-13 16:07:36 +00:00
Krzysztof Parzyszek fe0f895a8f [Hexagon] Re-enable machine verifier after codegen passes
Remove "false" from the arguments to "addPass" in Hexagon's target pass
config.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305015 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-08 21:25:36 +00:00
Chandler Carruth e3e43d9d57 Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line with a #include and let it re-sort things according to the precise
LLVM rules for include ordering baked into clang-format these days.

I've reverted a number of files where the results of sorting includes
isn't healthy. Either places where we have legacy code relying on
particular include ordering (where possible, I'll fix these separately)
or where we have particular formatting around #include lines that
I didn't want to disturb in this patch.

This patch is *entirely* mechanical. If you get merge conflicts or
anything, just ignore the changes in this patch and run clang-format
over your #include lines in the files.

Sorry for any noise here, but it is important to keep these things
stable. I was seeing an increasing number of patches with irrelevant
re-ordering of #include lines because clang-format was used. This patch
at least isolates that churn, makes it easy to skip when resolving
conflicts, and gets us to a clean baseline (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304787 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-06 11:49:48 +00:00
Matthias Braun 7d0dde023f TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFC
TargetPassConfig is not useful for targets that do not use the CodeGen
library, so we may just as well store a pointer to an
LLVMTargetMachine instead of just to a TargetMachine.

While at it, also change the constructor to take a reference instead of a
pointer as the TM must not be nullptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304247 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-30 21:36:41 +00:00
Francis Visoiu Mistrih ae1c853358 [LegacyPassManager] Remove TargetMachine constructors
This provides a new way to access the TargetMachine through
TargetPassConfig, as a dependency.

The patterns replaced here are:

* Passes handling a null TargetMachine call
  `getAnalysisIfAvailable<TargetPassConfig>`.

* Passes not handling a null TargetMachine
  `addRequired<TargetPassConfig>` and call
  `getAnalysis<TargetPassConfig>`.

* MachineFunctionPasses now use MF.getTarget().

* Remove all the TargetMachine constructors.
* Remove INITIALIZE_TM_PASS.

This fixes a crash when running `llc -start-before prologepilog`.

PEI needs StackProtector, which gets constructed without a TargetMachine
by the pass manager. The StackProtector pass doesn't handle the case
where there is no TargetMachine, so it segfaults.

Related to PR30324.

Differential Revision: https://reviews.llvm.org/D33222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303360 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-18 17:21:13 +00:00
Krzysztof Parzyszek d9552968c4 [Hexagon] Generate proper offset in opt-addr-mode
Also, make a few changes to allow using the pass in .mir testcases.
Among other things, change the abbreviation from opt-amode to amode-opt,
because otherwise lit would expand the "opt" part to the full path to
the opt binary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300707 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-19 15:15:51 +00:00
Reid Kleckner 6707770d48 Rename AttributeSet to AttributeList
Summary:
This class is a list of AttributeSetNodes corresponding the function
prototype of a call or function declaration. This class used to be
called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is
typically accessed by parameter and return value index, so
"AttributeList" seems like a more intuitive name.

Rename AttributeSetImpl to AttributeListImpl to follow suit.

It's useful to rename this class so that we can rename AttributeSetNode
to AttributeSet later. AttributeSet is the set of attributes that apply
to a single function, argument, or return value.

Reviewers: sanjoy, javed.absar, chandlerc, pete

Reviewed By: pete

Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits

Differential Revision: https://reviews.llvm.org/D31102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298393 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21 16:57:19 +00:00
Krzysztof Parzyszek e264bcdc06 [Hexagon] Add Hexagon-specific loop idiom recognition pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293213 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 21:41:10 +00:00
Mehdi Amini ae5f5d3d3c Move the global variables representing each Target behind accessor function
This avoids "static initialization order fiasco"

Differential Revision: https://reviews.llvm.org/D25412

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283702 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-09 23:00:34 +00:00
Krzysztof Parzyszek 9d1674fd71 [Hexagon] Change insertion of expand-condsets pass to avoid memory leaks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279678 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24 22:27:36 +00:00
Ron Lieberman 16082a39ea [Hexagon] Generate vector printing instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277370 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 19:36:39 +00:00
Brendon Cahoon c1359c9fbb MachinePipeliner pass that implements Swing Modulo Scheduling
Software pipelining is an optimization for improving ILP by
overlapping loop iterations. Swing Modulo Scheduling (SMS) is
an implementation of software pipelining that attempts to
reduce register pressure and generate efficient pipelines with
a low compile-time cost.

This implementaion of SMS is a target-independent back-end pass.
When enabled, the pass should run just prior to the register
allocation pass, while the machine IR is in SSA form. If the pass
is successful, then the original loop is replaced by the optimized
loop. The optimized loop contains one or more prolog blocks, the
pipelined kernel, and one or more epilog blocks.

This pass is enabled for Hexagon only. To enable for other targets,
a couple of target specific hooks must be implemented, and the
pass needs to be called from the target's TargetMachine
implementation.

Differential Review: http://reviews.llvm.org/D16829


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277169 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-29 16:44:44 +00:00
Krzysztof Parzyszek 5559171657 [Hexagon] Implement MI-level constant propagation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277028 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-28 20:01:59 +00:00
Krzysztof Parzyszek 262370bdcc [Hexagon] Use loop data prefetch on Hexagon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276422 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-22 14:22:43 +00:00
Krzysztof Parzyszek 8e211bbca8 [Hexagon] Do not create passes in the constructor of HexagonPassConfig
When running mir tests, a pass created in that constructor would not be
freed, leading to memory leaks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271043 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-27 20:48:39 +00:00
Rafael Espindola ac8db59598 Delete Reloc::Default.
Having an enum member named Default is quite confusing: Is it distinct
from the others?

This patch removes that member and instead uses Optional<Reloc> in
places where we have a user input that still hasn't been maped to the
default value, which is now clear has no be one of the remaining 3
options.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269988 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-18 22:04:49 +00:00
Krzysztof Parzyszek fcef736eb0 [Hexagon] Add a debug option to disable all backend optimizations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269192 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-11 15:01:30 +00:00
Matthias Braun 6a6190de10 CodeGen: Move TargetPassConfig from Passes.h to an own header; NFC
Many files include Passes.h but only a fraction needs to know about the
TargetPassConfig class. Move it into an own header. Also rename
Passes.cpp to TargetPassConfig.cpp while we are at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269011 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 03:21:59 +00:00
Krzysztof Parzyszek 744cc49078 [Hexagon] Optimize addressing modes for load/store
Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268051 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 15:49:13 +00:00
Krzysztof Parzyszek 1c960f5468 [Hexagon] Implement branch relaxation
Patch by Sirish Pande.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266792 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-19 18:30:18 +00:00
Krzysztof Parzyszek 626f833ad8 [Hexagon] Remove HexagonExpandPredSpillCode pass
This code is dead. The expansion is now done in HexagonFrameLowering.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260691 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-12 17:09:58 +00:00
Krzysztof Parzyszek 9f34dc17fe [Hexagon] Specify vector alignment in DataLayout string
The DataLayout can calculate alignment of vectors based on the alignment
of the element type and the number of elements. In fact, it is the product
of these two values. The problem is that for vectors of N x i1, this will
return the alignment of N bytes, since the alignment of i1 is 8 bits. The
vector types of vNi1 should be aligned to N bits instead. Provide explicit
alignment for HVX vectors to avoid such complications.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260678 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-12 14:47:38 +00:00
Krzysztof Parzyszek 5c562302c2 [Hexagon] Implement RDF-based post-RA optimizations
- Handle simple cases of register copies (what current RDF CP allows).
- Hexagon-specific dead code elimination: handles dead address updates
  in post-increment instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257504 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-12 19:09:01 +00:00
Krzysztof Parzyszek 468daaf55e [Hexagon] Subtarget features/default CPU corrections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255501 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-14 15:03:54 +00:00
Krzysztof Parzyszek c75a253689 [Hexagon] Bit-based instruction simplification
Analyze bit patterns of operands and values of instructions to perform
various simplifications, dead/redundant code elimination, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250868 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 22:57:13 +00:00
Krzysztof Parzyszek 62297b167d [Hexagon] Remove unnecessary argument sign extends
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250724 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 19:10:48 +00:00
Krzysztof Parzyszek c3d768d729 [Hexagon] Delay emission of CFI instructions
Emit the CFI instructions after all code transformation have been done.
This will avoid any interference between CFI instructions and packetization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250714 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 17:46:01 +00:00
Krzysztof Parzyszek 9bad2f04b3 [Hexagon] Split double registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250549 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-16 20:38:54 +00:00
Krzysztof Parzyszek 477d91f460 [Hexagon] Delete lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250543 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-16 19:51:53 +00:00
Krzysztof Parzyszek 466f9e2f0c [Hexagon] Merge adjacent stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250542 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-16 19:43:56 +00:00
Krzysztof Parzyszek 42c0741b0d [Hexagon] Add an early if-conversion pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249423 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-06 15:49:14 +00:00
Eric Christopher 973f7aa32a constify the Function parameter to the TTI creation callback and
propagate to all callers/users/etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247864 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 23:38:13 +00:00