1894 Commits

Author SHA1 Message Date
Florian Hahn 545ec94b43 [AArch64] Fix -mcpu option in aarch64-combine-fmul-fsub.mir (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321865 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-05 11:17:48 +00:00
Aditya Nandakumar 09d2d44675 [GISel]: Don't create G_MUL with 1 during translation of GEP
When element size is 1, it's just wasteful to create MUL with 1.
https://reviews.llvm.org/D41738

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321857 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-05 02:56:28 +00:00
Evandro Menezes b3a26d8ca6 [AArch64] Improve code generation of vector build
Instead of using, for example, `dup v0.4s, wzr`, which transfers between
register files, use the more efficient `movi v0.4s, #0` instead.

Differential revision: https://reviews.llvm.org/D41515

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321824 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-04 21:43:12 +00:00
Amara Emerson caeab26ff8 [GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflow
Previously the code for handling G_SMULO didn't properly check for the signed
multiply overflow, instead treating it the same as the unsigned G_UMULO.

Fixes PR35800.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321690 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03 04:56:56 +00:00
Sanjay Patel 0a935b3a90 [AArch64] fix typos in comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321673 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 21:04:08 +00:00
Sanjay Patel db850cf9f4 [ValueTracking] recognize min/max of min/max patterns
This is part of solving PR35717:
https://bugs.llvm.org/show_bug.cgi?id=35717

The larger IR optimization is proposed in D41603, but we can show 
the improvement in ValueTracking using codegen tests because 
SelectionDAG creates min/max nodes based on ValueTracking. 

Any target with min/max ops should show wins here. I chose AArch64
vector ops because they're clean and uniform.

Some Alive proofs for the tests (can't put more than 2 tests in 1 
page currently because the web app says it's too long):
https://rise4fun.com/Alive/WRN
https://rise4fun.com/Alive/iPm
https://rise4fun.com/Alive/HmY
https://rise4fun.com/Alive/CNm
https://rise4fun.com/Alive/LYf



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321672 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 20:56:45 +00:00
Sanjay Patel 6ae0f3914e [AArch64] add tests for min/max of min/max (PR35717); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321668 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 20:16:45 +00:00
Amara Emerson 7b20f91f4d [AArch64][GlobalISel] Fix assert fail with unknown intrinsic.
A call may have an intrinsic name but not have a valid intrinsic ID,
for example with llvm.invariant.group.barrier. If so, treat it as a
normal call like FastISel does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321662 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 18:56:39 +00:00
Amara Emerson d8de4cebd9 [AArch64][GlobalISel] Enable GlobalISel at -O0 by default
Tests updated to explicitly use fast-isel at -O0 instead of implicitly.

This change also allows an explicit -fast-isel option to override an
implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0.

Differential Revision: https://reviews.llvm.org/D41362

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321655 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 16:30:47 +00:00
Daniel Jasper 7f55be51ae Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204)
Our internal testing has revealed has discovered bugs in PPC builds.
I have forward reproduction instructions to the original author (Nirav).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321649 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02 14:38:52 +00:00
Matthew Simpson baeee310cc [AArch64] Change order of candidate FMLS patterns
r319980 added new patterns to the machine combiner for transforming (fsub (fmul
x y) z) into (fmla (fneg z) x y). That is, fsub's where the first source
operand is an fmul are transformed. We previously only matched the case where
the second source operand of an fsub was an fmul, transforming (fsub z (fmul x
y)) into (fmls z x y). Now, if we have an fsub where both source operands are
fmuls, both of the above patterns are applicable.

However, the order in which we add the patterns to the list of candidates
determines the transformation that takes place, since only the first pattern
that matches will be used. This patch changes the order these two patterns are
added to the list of candidates such that we prefer the case where the second
source operand is an fmul (the fmls case), rather than the other one (the
fmla/fneg case). When both source operands are fmuls, this ordering results in
fewer instructions.

Differential Revision: https://reviews.llvm.org/D41587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321491 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-27 15:25:01 +00:00
Simon Pilgrim ff53894326 [DAGCombine] visitANDLike - ensure APInt is is in range for getSExtValue/getZExtValue
Reduced from oss-fuzz #4782 test case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321464 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-26 23:27:44 +00:00
Michael Zolotukhin 7f4699ff8f [SimplifyCFG] Avoid quadratic on a predecessors number behavior in instruction sinking.
If a block has N predecessors, then the current algorithm will try to
sink common code to this block N times (whenever we visit a
predecessor). Every attempt to sink the common code includes going
through all predecessors, so the complexity of the algorithm becomes
O(N^2).
With this patch we try to sink common code only when we visit the block
itself. With this, the complexity goes down to O(N).
As a side effect, the moment the code is sunk is slightly different than
before (the order of simplifications has been changed), that's why I had
to adjust two tests (note that neither of the tests is supposed to test
SimplifyCFG):
* test/CodeGen/AArch64/arm64-jumptable.ll - changes in this test mimic
the changes that previous implementation of SimplifyCFG would do.
* test/CodeGen/ARM/avoid-cpsr-rmw.ll - in this test I disabled common
code sinking by a command line flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321236 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21 01:22:13 +00:00
Tim Northover d2c80d9fc1 AArch64: fix one more place movi.2d could be created.
Somehow got missed out of r320965.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321162 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-20 10:45:39 +00:00
Martin Storsjo c8f103e52b [AArch64] Implement stack probing for windows
Differential Revision: https://reviews.llvm.org/D41131

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321150 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-20 06:51:45 +00:00
Francis Visoiu Mistrih 30e8e017c8 [CodeGen] Move printing MO_FPImmediate operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321110 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-19 21:47:00 +00:00
Amara Emerson ea090c0f0e [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types.
This doesn't add legalizer support, just prevents crashing so that we
can gracefully fall back to SDAG.

Fixes PR35690.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321091 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-19 17:21:35 +00:00
Nirav Dave e63c3fb2b2 [DAG] Elide overlapping store
Summary:
Extend overlapping store elision to handle overwrites of stores by
larger stores.

Nontemporal tests have been modified to add memory dependencies to
prevent store elision.

Reviewers: craig.topper, rnk, t.p.northover

Subscribers: javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321089 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-19 17:10:56 +00:00
Justin Bogner 437b240ff1 update_mir_test_checks: Accept IR as input as well as MIR
We need to handle IR for tests that want to do lowering (or just
-stop-after with IR as input). I've run this on one AArch64 test to
demonstrate what it looks like.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321048 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-19 00:49:04 +00:00
Matthias Braun 51a1d9adb9 TargetLoweringBase: Followup to r321035
I missed some prefixes and the fact that on AArch64 we use "bzero"
instead of "__bzero" as on X86 when doing my refactoring in r321035.

Improve tests for bzero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321046 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-19 00:43:00 +00:00
Evandro Menezes 456d2793cd [AArch64] Expand test coverage of vector element shuffling to Exynos
Make sure that all test cases are run for Exynos as well.  Otherwise, NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321032 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-18 22:17:39 +00:00
Jessica Paquette d4a00a6773 [MachineOutliner] Recommit r320229
LR was undefined entering outlined functions that contain calls. This made the
machine verifier unhappy when expensive checks were enabled. This fixes that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321014 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-18 19:33:21 +00:00
Tim Northover f66f36e9a4 AArch64: work around how Cyclone handles "movi.2d vD, #0".
For Cylone, the instruction "movi.2d vD, #0" is executed incorrectly in some rare
circumstances. Work around the issue conservatively by avoiding the instruction entirely.

This patch changes CodeGen so that problematic instructions are never
generated, and the AsmParser so that an equivalent instruction is used (with a
warning).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320965 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-18 10:36:00 +00:00
Francis Visoiu Mistrih 38e881da88 [CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`%stack.0` instead of `<fi#0>`, and `%fixed-stack.0` instead of
`<fi#-4>` (supposing there are 4 fixed stack objects).

Only debug syntax is affected.

Differential Revision: https://reviews.llvm.org/D41027

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320827 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15 16:33:45 +00:00
Francis Visoiu Mistrih 3f63013fb4 [CodeGen] Print global addresses as @foo in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`@foo` instead of `<ga:@foo>`.

Also print target flags in the MIR format since most of them are used on
global address operands.

Only debug syntax is affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320682 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 10:03:09 +00:00
Galina Kistanova e8e0a7cf7b Reverted r320229. It broke tests on builder llvm-clang-x86_64-expensive-checks-win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320588 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 15:26:27 +00:00
Francis Visoiu Mistrih d347e9783d [CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`.

Only debug syntax is affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320566 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 10:30:59 +00:00
Geoff Berry 3b391fe80e [MachineOperand][MIR] Add isRenamable to MachineOperand.
Summary:
Add isRenamable() predicate to MachineOperand.  This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand.  Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).

Reviewers: qcolombet, MatzeB, hfinkel

Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D39400

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320503 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12 17:53:59 +00:00
Amara Emerson 4feece4289 [GlobalISel] Disable GISel for big endian.
This is due to PR26161 needing to be resolved before we can fix
big endian bugs like PR35359. The work to split aggregates into smaller LLTs
instead of using one large scalar will take some time, so in the mean time
we'll fall back to SDAG.

Some ARM BE tests xfailed for now as a result.

Differential Revision: https://reviews.llvm.org/D40789

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320388 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-11 16:58:29 +00:00
Joel Jones 14ef3034c4 [AArch64] Improve loop unrolling performance on Cavium T99
This patch improves performance on Cavium T99 as shown here (libquantum 0.2.4):

https://docs.google.com/spreadsheets/d/1Lo1o2E1NjrpkwS7DvYYWsiVvPdd93h7KBaqeptMrZPY/edit?usp=sharing

By increasing the LoopMicroOpsBufferSize in the Cavium T99 Scheduler file,
loop unrolling becomes more aggressive. This helps performance on T99.

Test case included.

Patch by Stefan Teleman

Differential Revision: https://reviews.llvm.org/D40695 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320272 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-09 23:59:55 +00:00
Jessica Paquette ce39caef81 [MachineOutliner] Outline calls
The outliner previously would never outline calls. Calls are pretty common in
files, so it makes sense to outline them. In fact, in the LLVM test suite, if
you count the number of instructions that the outliner misses when you outline
calls vs when you don't, it turns out that, on average, around 6% of the
instructions encountered are calls. So, if we outline calls, we can find more
candidates, and thus save some more space.

This commit adds that functionality and updates the mir test to reflect that.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320229 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-09 00:43:49 +00:00
Abderrazek Zaafrani 94240acddc [AArch64] Avoid SIMD interleaved store instruction for Exynos.
Replace interleaved store instructions by equivalent and more efficient instructions based on latency cost model.
Https://reviews.llvm.org/D38196

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320123 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-08 00:58:49 +00:00
Jessica Paquette c297153c36 [MachineOutliner] Fix offset overflow check
The offset overflow check before was incorrect. It would always give the
correct result, but it was comparing the SCALED potential fixed-up offset
against an UNSCALED minimum/maximum. As a result, the outliner was missing a
bunch of frame setup/destroy instructions that ought to have been safe to
outline. This fixes that, and adds an instruction to the .mir test that
failed the old test.
  


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320090 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-07 21:51:43 +00:00
Francis Visoiu Mistrih fd11bc0813 [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
Work towards the unification of MIR and debug output by refactoring the
interfaces.

For MachineOperand::print, keep a simple version that can be easily called
from `dump()`, and a more complex one which will be called from both the
MIRPrinter and MachineInstr::print.

Add extra checks inside MachineOperand for detached operands (operands
with getParent() == nullptr).

https://reviews.llvm.org/D40836

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320022 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-07 10:40:31 +00:00
Florian Hahn f42965e37e [AArch64] Add patterns to replace fsub fmul with fma fneg.
Summary:
This patch adds MachineCombiner patterns for transforming
(fsub (fmul x y) z) into (fma x y (fneg z)). This has a lower
latency on micro architectures where fneg is cheap.

Patch based on work by George Steed.

Reviewers: rengolin, joelkevinjones, joel_k_jones, evandro, efriedma

Reviewed By: evandro

Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40306

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319980 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-06 22:48:36 +00:00
Nirav Dave 256a26609b [ARM][AArch64][DAG] Reenable post-legalize store merge
Reenable post-legalize stores with constant merging computation and
corresponding test case.

 * Properly truncate store merge constants
 * Disable merging of truncated stores floating points
 * Ensure merges of constant stores into a single vector are
   constructed from legal elements.

Reviewers: eastig, efriedma

Reviewed By: eastig

Subscribers: spatel, rengolin, aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40701

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319899 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-06 15:30:13 +00:00
Daniel Sanders 02ef0610a9 Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.
Some concerns were raised with the direction. Revert while we discuss it and look into an alternative



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319739 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05 05:52:07 +00:00
Daniel Sanders 67fbf95b76 [globalisel][tablegen] Tests for r319691
I forgot to 'svn add' the test files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319698 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 21:14:34 +00:00
Daniel Sanders e35711676b [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.
This patch splits atomics out of the generic G_LOAD/G_STORE and into their own
G_ATOMIC_LOAD/G_ATOMIC_STORE. This is a pragmatic decision rather than a
necessary one. Atomic load/store has little in implementation in common with
non-atomic load/store. They tend to be handled very differently throughout the
backend. It also has the nice side-effect of slightly improving the common-case
performance at ISel since there's no longer a need for an atomicity check in the
matcher table.

All targets have been updated to remove the atomic load/store check from the
G_LOAD/G_STORE path. AArch64 has also been updated to mark
G_ATOMIC_LOAD/G_ATOMIC_STORE legal.

There is one issue with this patch though which also affects the extending loads
and truncating stores. The rules only match when an appropriate G_ANYEXT is
present in the MIR. For example,
  (G_ATOMIC_STORE (G_TRUNC:s16 (G_ANYEXT:s32 (G_ATOMIC_LOAD:s16 X))))
will match but:
  (G_ATOMIC_STORE (G_ATOMIC_LOAD:s16 X))
will not. This shouldn't be a problem at the moment, but as we get better at
eliminating extends/truncates we'll likely start failing to match in some
cases. The current plan is to fix this in a patch that changes the
representation of extending-load/truncating-store to allow the MMO to describe
a different type to the operation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319691 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 20:39:32 +00:00
Francis Visoiu Mistrih ca0df55065 [CodeGen] Unify MBB reference format in both MIR and debug output
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 17:18:51 +00:00
Martin Storsjo ed04373440 [AArch64] Allow using emulated tls on platforms other than ELF
This matches how it is done on X86.

This allows using emulated tls on windows; in MinGW environments,
native tls isn't supported at the moment.

Set the right Data*bitsDirective for windows to match the existing
tests for other platforms. Make parts of the existing tests a regex,
to allow matching .section .rdata for windows, to avoid having to
duplicate the rest of the tests for windows.

Differential Revision: https://reviews.llvm.org/D40770

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319644 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 09:09:04 +00:00
Nirav Dave deae672db6 [DAG][AArch64] Disable post-legalization store
Disable post-legalization store for AArch64 backend which is causing
errors out-of-tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319607 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 04:01:26 +00:00
Adam Nemet c4f204db88 [opt-remarks] If hotness threshold is set, ignore remarks without hotness
These are blocks that haven't not been executed during training.  For large
projects this could make a significant difference.  For the project, I was
looking at, I got an order of magnitude decrease in the size of the total YAML
files with this and r319235.

Differential Revision: https://reviews.llvm.org/D40678

Re-commit after fixing the failing testcase in rL319576, rL319577 and
rL319578.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319581 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 20:41:38 +00:00
Adam Nemet 53cc245050 Revert "[opt-remarks] If hotness threshold is set, ignore remarks without hotness"
This reverts commit r319556.

Something is not working with this when used with sample-based profiling.
Investigating...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319562 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 18:12:29 +00:00
Adam Nemet 7cb910a453 [opt-remarks] If hotness threshold is set, ignore remarks without hotness
These are blocks that haven't not been executed during training.  For large
projects this could make a significant difference.  For the project, I was
looking at, I got an order of magnitude decrease in the size of the total YAML
files with this and r319235.

Differential Revision: https://reviews.llvm.org/D40678

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319556 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 17:02:04 +00:00
Volkan Keles af9296a79c GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUES
Summary: LegalizerInfo assumes all G_MERGE_VALUES and G_UNMERGE_VALUES instructions are legal, so it is not possible to legalize vector operations on illegal vector types. This patch fixes the problem by removing the related check and adding default actions for G_MERGE_VALUES and G_UNMERGE_VALUES.

Reviewers: qcolombet, ab, dsanders, aditya_nandakumar, t.p.northover, kristof.beyls

Reviewed By: dsanders

Subscribers: rovka, javed.absar, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D39823

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319524 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 08:19:10 +00:00
Daniel Sanders 0ba92ff15e [aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_*
G_ATOMICRMW_* is generally legal on AArch64. The exception is G_ATOMICRMW_NAND.

G_ATOMIC_CMPXCHG_WITH_SUCCESS needs to be lowered to G_ATOMIC_CMPXCHG with an
external comparison.

Note that IRTranslator doesn't generate these instructions yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319466 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30 20:11:42 +00:00
Amara Emerson ff7abc1a3f [GlobalISel][IRTranslator] Fix crash during translation of zero sized loads/stores/args/returns.
This fixes PR35358.

rdar://35619533

Differential Revision: https://reviews.llvm.org/D40604

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319465 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30 20:06:02 +00:00
Francis Visoiu Mistrih e6b89910eb [CodeGen] Always use printReg to print registers in both MIR and debug
output

As part of the unification of the debug format and the MIR format,
always use `printReg` to print all kinds of registers.

Updated the tests using '_' instead of '%noreg' until we decide which
one we want to be the default one.

Differential Revision: https://reviews.llvm.org/D40421

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319445 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30 16:12:24 +00:00
Francis Visoiu Mistrih 7384652668 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).

Basically:

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed

Differential Revision: https://reviews.llvm.org/D40420

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319427 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30 12:12:19 +00:00