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3 Commits

Author SHA1 Message Date
Alex Bradbury 26132ea8ed [RISCV] Add support for all RV32I instructions 
This patch supports all RV32I instructions as described in the RISC-V manual.
A future patch will add support for pseudoinstructions and other instruction
expansions (e.g. 0-arg fence -> fence iorw, iorw).

Differential Revision: https://reviews.llvm.org/D23566


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313485 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-09-17 14:27:35 +00:00
Alex Bradbury 6e8164d525 [RISCV] Trivial whitespace fix in RISCVInstPrinter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311277 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-20 06:58:43 +00:00
Alex Bradbury 1de4891dd5 [RISCV] Add RISCVInstPrinter and basic MC assembler tests 
With the addition of RISCVInstPrinter, it is now possible to test the basic 
operation of the RISCV MC layer.

Differential Revision: https://reviews.llvm.org/D23564


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310917 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-15 13:08:29 +00:00