f333491832
[mips] Use --check-prefixes where appropriate. NFC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273669 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-24 12:23:17 +00:00
98d31c1b79
[mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions
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Differential Revision: http://reviews.llvm.org/D16917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272876 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-16 07:06:25 +00:00
d72ba1af57
[mips] Optimize code generation for 64-bit variable shift instructions.
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Summary:
The 64-bit version of the variable shift instructions uses the
shift_rotate_reg class which uses a GPR32Opnd to specify the variable
shift amount. With this patch we avoid the generation of a redundant
SLL instruction for the variable shift instructions in 64-bit targets.
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235376 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21 10:49:03 +00:00
ee973147ac
Remove definitions of double word shift plus 32 instructions. Assembler or
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direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:44:09 +00:00
c7bafe9241
Add definitions of Mips64 rotate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 18:51:46 +00:00
d80c13bfed
Check values of immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140860 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 17:19:21 +00:00
25a7d94e81
Mips64 shift instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 03:18:46 +00:00
Daniel Sanders