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65 Commits

Author SHA1 Message Date
Jim Grosbach
997759ac22 Add source Record* reference to PatternToMatch. Allows better diagnostics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121196 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 23:05:49 +00:00
Jim Grosbach
45258f5708 Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 19:36:07 +00:00
Jim Grosbach
76612b549f Change assert to diagnostic. Message still needs work, but it's better than 
an assert, at least.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121166 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-07 19:35:36 +00:00
Chris Lattner
c240bb0ede factor the operand list (and related fields/operations) out of 
CodeGenInstruction into its own helper class.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-01 04:03:32 +00:00
Eric Christopher
53452606ca Allow strict subclasses of register classes, this way we can handle 
ARM instructions with:

foo GPR, rGPR

which happens a lot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112025 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 04:58:56 +00:00
Eric Christopher
2cfcad97b7 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111996 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 23:21:59 +00:00
Eric Christopher
922157c834 Remove predicate workaround, we're going to require that predicate 
and optional def operands are handled in the backend support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111220 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 01:18:37 +00:00
Eric Christopher
bc16827be6 Filter out patterns that have PredicateOperands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109572 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-28 01:52:23 +00:00
Eric Christopher
ecfa079206 80-col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109407 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-26 17:53:07 +00:00
Eric Christopher
07fdd897e2 Hack around extracts that aren't easy to process. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109043 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-21 22:07:19 +00:00
Jakob Stoklund Olesen
4f8e771ae8 Replace copyRegToReg with COPY in FastISelEmitter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108071 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-11 03:53:50 +00:00
Dan Gohman
84023e0fbe Reapply bottom-up fast-isel, with several fixes for x86-32: 
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-10 09:00:22 +00:00
Bob Wilson
02266e29f9 --- Reverse-merging r107947 into '.': 
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 16:37:18 +00:00
Dan Gohman
a5d4391d6d These changes should have accompanied r107943. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-09 00:59:16 +00:00
Dan Gohman
f595141525 Revert 107840 107839 107813 107804 107800 107797 107791. 
Debug info intrinsics win for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 01:00:56 +00:00
Dan Gohman
eabaed26c3 Give FunctionLoweringInfo an MBB member, avoiding the need to pass it 
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 16:47:08 +00:00
Dan Gohman
098d3a41e1 Minor code simplification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 16:25:05 +00:00
Jakob Stoklund Olesen
73ea7bf450 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 14:48:12 +00:00
Dan Gohman
a6cb641f48 Add initial kill flag support to FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 23:54:07 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:33:48 +00:00
Chris Lattner
084df627c8 add plumbing for handling multiple result nodes 
in some more places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99366 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 00:41:19 +00:00
Chris Lattner
d734919465 major surgery on tblgen: generalize TreePatternNode 
to maintain a list of types (one for each result of
the node) instead of a single type.  There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98999 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 21:37:09 +00:00
Chris Lattner
f30187a363 look up instructions by record, not by name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 00:07:20 +00:00
Chris Lattner
2cacec55f9 Completely rewrite tblgen's type inference mechanism, 
changing the primary datastructure from being a 
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input 
values agree in type with their output values.

This also eliminates code that transparently assumes (in 
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no 
functionality change!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98534 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-15 06:00:16 +00:00
Dan Gohman
7c3ecb6838 Don't use the ISD::NodeType enum for SDNode opcodes, as CodeGen 
uses several kinds of opcode values which are not declared within
that enum. This fixes PR5946.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 22:26:32 +00:00
Duncan Sands
b7c5bdf843 Remove some unused variables and methods warned about by 
icc (#177, partial).  Patch by Erick Tryzelaar.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81106 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-06 08:33:48 +00:00
Owen Anderson
825b72b057 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 20:47:22 +00:00
Owen Anderson
e50ed30282 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-10 22:56:29 +00:00
Daniel Dunbar
1a55180238 Replace std::iostreams with raw_ostream in TableGen. 
- Sorry, I can't help myself.

 - No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-03 00:10:29 +00:00
Dale Johannesen
edc8774a73 TableGen for fast isel seems to assume an 'imm' 
operand is the last in a pattern.  There is no
reason this should be true (although apparently
it always is right now).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72232 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-21 22:25:49 +00:00
Evan Cheng
536ab130ec Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-22 09:10:11 +00:00
Dan Gohman
0540e17788 Add support for having multiple predicates on a TreePatternNode. 
This will allow predicates to be composed, which will allow the
predicate definitions to become less redundant, and eventually
will allow DAGISelEmitter.cpp to emit less redundant code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57562 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-15 06:17:21 +00:00
Dan Gohman
5ec9efd61b Move the primary fast-isel top-level comments to FastISel.cpp, where 
they'll be a little more visible. Also, update and reword them a bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56877 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-30 20:48:29 +00:00
Evan Cheng
98d2d07d41 Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55893 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-08 08:39:33 +00:00
Evan Cheng
d07b46e908 Fix indentation of generated code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55876 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-07 08:23:06 +00:00
Evan Cheng
34fc6ceb73 Ignore multi-instruction patterns. e.g. 
def : Pat<(i8 (trunc GR32:$src)),
          (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55875 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-07 08:19:51 +00:00
Evan Cheng
c3f44b0d63 Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55679 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 00:03:49 +00:00
Owen Anderson
667d8f7607 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 17:45:56 +00:00
Dan Gohman
99b218218c Add a target callback for FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:21:34 +00:00
Owen Anderson
b5dbcb538b Add support for fast-isel of opcodes that require use of extract_subreg. Because of how extract_subreg is treated, it requires special case handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55480 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 18:06:12 +00:00
Dan Gohman
833ddf8430 Update a comment to reflect recent changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55418 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 16:18:22 +00:00
Dan Gohman
10df0fa73e Basic FastISel support for floating-point constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55401 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 01:09:54 +00:00
Dan Gohman
72d63af3f7 Refactor a bunch of FastISelEmitter code into a helper class, and 
put each major step in a separate function. This makes the high
level sequence of events easier to follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55385 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 21:21:20 +00:00
Owen Anderson
70647e81e3 We need to check that the return type is correct, even in cases where we don't 
have a return type that differs from the operand types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55376 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 18:50:00 +00:00
Owen Anderson
abb1f16881 Throw the switch to allow FastISel to emit instructions whose return types different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55349 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 01:22:59 +00:00
Owen Anderson
71669e51e5 Enhance TableGen to emit code for FastISel of opcodes with variadic return types without slowing down opcodes that are not variadic. No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55347 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 00:42:26 +00:00
Owen Anderson
0f84e4e310 Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return 
type down.  This is not currently used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55345 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 23:58:18 +00:00
Owen Anderson
7b2e579546 Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns 
with return types that differ from their input types.  This is not yet used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55344 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 23:43:09 +00:00
Owen Anderson
6d0c25ec3a Add support for fast isel of (integer) immediate materialization pattens, and use them to support 
bitcast of constants in fast isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55325 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 20:20:32 +00:00
Dan Gohman
0bfb75277f Add a few comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55157 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 00:28:15 +00:00