Commit Graph

27 Commits

Author SHA1 Message Date
Yaxun Liu
ab3be33d40 [AMDGPU] Get address space mapping by target triple environment
As we introduced target triple environment amdgiz and amdgizcl, the address
space values are no longer enums. We have to decide the value by target triple.

The basic idea is to use struct AMDGPUAS to represent address space values.
For address space values which are not depend on target triple, use static
const members, so that they don't occupy extra memory space and is equivalent
to a compile time constant.

Since the struct is lightweight and cheap, it can be created on the fly at
the point of usage. Or it can be added as member to a pass and created at
the beginning of the run* function.

Differential Revision: https://reviews.llvm.org/D31284


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298846 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-27 14:04:01 +00:00
Matt Arsenault
0b229143d8 AMDGPU: Remove llvm.AMDGPU.cube intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295359 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-16 19:09:04 +00:00
Jan Vesely
5709854b8d AMDGPU/R600: Serialize vector trunc stores to private AS
Add DUMMY_CHAIN SDNode to denote stores of interest

Bugzilla: https://llvm.org/bugs/show_bug.cgi?id=28915
Bugzilla: https://llvm.org/bugs/show_bug.cgi?id=30411

Differential Revision: https://reviews.llvm.org/D27964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292651 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-20 21:24:26 +00:00
Jan Vesely
0835374acb AMDGPU/R600: Don't use REGISTER_{LOAD,STORE} ISD nodes
This will make transition to SCRATCH_MEMORY easier

Differential Revision: https://reviews.llvm.org/D24746

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291279 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-06 21:00:46 +00:00
Matt Arsenault
350d0dab1e AMDGPU: Refactor exp instructions
Structure the definitions a bit more like the other classes.

The main change here is to split EXP with the done bit set
to a separate opcode, so we can set mayLoad = 1 so that it won't
be reordered before the other exp stores, since this has the special
constraint that if the done bit is set then this should be the last
exp in she shader.

Previously all exp instructions were inferred to have unmodeled
side effects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288695 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-05 20:23:10 +00:00
Peter Collingbourne
a425991140 Target: Remove unused patterns and transforms. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283515 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-07 00:30:49 +00:00
Matt Arsenault
95ec13b22a AMDGPU: Select mulhi 24-bit instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279902 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 01:32:27 +00:00
Jan Vesely
fc94e66b10 AMDGPU/R600: Convert buffer id to VTX_READ input
Use patterns instead of multiple instructions
Add buffer id to asm string

https://reviews.llvm.org/D22650

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278749 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-15 21:38:30 +00:00
Matt Arsenault
5fecfa22e5 AMDGPU: Fix TargetPrefix for remaining r600 intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275619 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 21:27:08 +00:00
Matt Arsenault
7150fbf236 AMDGPU: Remove legacy rsq.clamped intrinsic
Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining.

Also fix mismatch with non-IEEE rsq selecting to IEEE rsq.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275617 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 21:26:52 +00:00
Matt Arsenault
4d120e9b24 AMDGPU/R600: Delete/rename intrinsics no longer used by mesa
Use the replacement pass to update the tests, and delete old names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275375 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-14 05:47:17 +00:00
Matt Arsenault
04e6d2604d AMDGPU/R600: Remove intrinsics with no tests and no users
Mesa removed this path, so nothing is using these anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275372 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-14 05:23:23 +00:00
Jan Vesely
e2b4643334 AMDGPU/R600: Add implicitarg.ptr intrinsic
Differential Revision: http://reviews.llvm.org/D21622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275024 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-10 21:20:29 +00:00
Tom Stellard
25cd212829 AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loads
This moves of the r600 logic out of isGlobalLoad() and into the
TableGen files.

Differential Revision: http://reviews.llvm.org/D21710

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274527 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-05 00:12:51 +00:00
Jan Vesely
fa06bbbcab AMDGPU/R600: Add indentation to VTX and TEX fetch asm strings
These are printed as part of Fetch clauses.

Differential Revision: http://reviews.llvm.org/D21730

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274517 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-04 19:45:00 +00:00
Matt Arsenault
759ed7e410 AMDGPU: Cleanup subtarget handling.
Split AMDGPUSubtarget into amdgcn/r600 specific subclasses.
This removes most of the static_casting of the basic codegen
classes everywhere, and tries to restrict the features
visible on the wrong target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273652 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-24 06:30:11 +00:00
Matt Arsenault
e22857013f AMDGPU: Fix verifier errors in SILowerControlFlow
The main sin this was committing was using terminator
instructions in the middle of the block, and then
not updating the block successors / predecessors.
Split the blocks up to avoid this and introduce new
pseudo instructions for branches taken with exec masking.

Also use a pseudo instead of emitting s_endpgm and erasing
it in the special case of a non-void return.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273467 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-22 20:15:28 +00:00
Jan Vesely
fbff874b03 AMDGPU/R600: Implement memory loads from constant AS
Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19792

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269479 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 20:39:29 +00:00
Matt Arsenault
a4c1dc826a AMDGPU: Rename intrinsic to better match instruction name
Also fixes missing f32 test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260780 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-13 01:03:00 +00:00
Matt Arsenault
3d679fa973 AMDGPU: Remove 24-bit intrinsics
The known bit matching code seems to work reasonably well,
so these shouldn't really be needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@259180 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-29 10:05:16 +00:00
Matt Arsenault
78c5400038 AMDGPU: Remove more unused intrinsics
Replace tests with lrp with basic IR expansion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258612 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-23 05:42:38 +00:00
Matt Arsenault
3e81c4eb9a AMDGPU: Remove random TGSI intrinsic
I don't think this was ever used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258514 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-22 18:42:44 +00:00
Matt Arsenault
eb3f71fe95 AMDGPU: Remove AMDGPU.fract intrinsic
Mesa doesn't use this, and this is pattern matched already
from fsub x, (ffloor x)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-22 18:42:38 +00:00
Bruce Mitchener
767c34a919 Fix typos.
Summary: This fixes a variety of typos in docs, code and headers.

Subscribers: jholewinski, sanjoy, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12626

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247495 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-12 01:17:08 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00
Tom Stellard
b1162b8d4b Revert "AMDGPU: Add core backend files for R600/SI codegen v6"
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:53 +00:00
Tom Stellard
23dc769a9b AMDGPU: Add core backend files for R600/SI codegen v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 14:17:08 +00:00