Commit Graph

22 Commits

Author SHA1 Message Date
Matt Arsenault 2f65ff664c AMDGPU/R600: Implement allowsMisalignedMemoryAccess
This avoids some test regressions in a future commit
when unaligned operations are expanded when they
have custom lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261570 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-22 21:04:16 +00:00
Matt Arsenault a4c1dc826a AMDGPU: Rename intrinsic to better match instruction name
Also fixes missing f32 test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260780 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-13 01:03:00 +00:00
Matt Arsenault b49a0edca2 AMDGPU: Split R600 and SI store lowering
These were only sharing some somewhat incorrect
logic for when to scalarize or split vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260490 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-11 05:32:46 +00:00
Matt Arsenault e6640ee461 AMDGPU: Split R600 and SI load lowering
These weren't actually sharing anything in the common
LowerLOAD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260398 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-10 18:21:39 +00:00
Ahmed Bougacha 3248c624fa [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260316 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-09 22:54:12 +00:00
Matt Arsenault ae4d40b742 AMDGPU: Restore AMDGPU prefixed rsq intrinsic for now
Also move into backend intrinsics to discourage use of the old name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258783 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-26 04:14:16 +00:00
Matt Arsenault 78c5400038 AMDGPU: Remove more unused intrinsics
Replace tests with lrp with basic IR expansion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258612 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-23 05:42:38 +00:00
Matt Arsenault faf8ffaefd AMDGPU: Rename intrinsics to use amdgcn prefix
The intrinsic target prefix should match the target name
as it appears in the triple.

This is not yet complete, but gets most of the important ones.
llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled
for compatability for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258557 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-22 21:30:34 +00:00
Matt Arsenault a75de8d6ed AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix
These ones aren't directly emitted by mesa and inserted by a pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258523 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-22 19:00:09 +00:00
Matt Arsenault 21559cea5b AMDGPU: Remove unused R600 intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258522 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-22 18:52:14 +00:00
Matt Arsenault eb3f71fe95 AMDGPU: Remove AMDGPU.fract intrinsic
Mesa doesn't use this, and this is pattern matched already
from fsub x, (ffloor x)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-22 18:42:38 +00:00
Matt Arsenault 1cbcadaf34 AMDGPU: Remove AMDIL.fraction intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258347 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-20 21:05:49 +00:00
Tom Stellard 7fe09ce82f AMDGPU: Add MEM_RAT STORE_TYPED.
v2: Add test (Matt).
    Fix capitalization of isEOP (Matt).
    Move pattern to class parameter (Matt).
    Make the instruction available to Cayman (Matt).
    Change name from MEM_RAT WRITE_TYPED to MEM_RAT STORE_TYPED.

Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249042 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-01 17:51:34 +00:00
Tom Stellard e53ca97014 AMDGPU: Factor out EOP query.
v2: Fix brace placement and capitalization (Matt).

Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249041 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-01 17:51:29 +00:00
Sanjay Patel 39490133e4 propagate fast-math-flags on DAG nodes
After D10403, we had FMF in the DAG but disabled by default. Nick reported no crashing errors after some stress testing, 
so I enabled them at r243687. However, Escha soon notified us of a bug not covered by any in-tree regression tests: 
if we don't propagate the flags, we may fail to CSE DAG nodes because differing FMF causes them to not match. There is
one test case in this patch to prove that point.

This patch hopes to fix or leave a 'TODO' for all of the in-tree places where we create nodes that are FMF-capable. I 
did this by putting an assert in SelectionDAG.getNode() to find any FMF-capable node that was being created without FMF
( D11807 ). I then ran all regression tests and test-suite and confirmed that everything passes.

This patch exposes remaining work to get DAG FMF to be fully functional: (1) add the flags to non-binary nodes such as
FCMP, FMA and FNEG; (2) add the flags to intrinsics; (3) use the flags as conditions for transforms rather than the
current global settings.

Differential Revision: http://reviews.llvm.org/D12095



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247815 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 16:31:21 +00:00
Mehdi Amini e03f4bd255 Add missing break in switch case in R600ISelLowering
Summary: Catched by coverity.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11120

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242388 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 06:23:12 +00:00
Tom Stellard 847c023a2e AMDGPU: Add helper function for implicit parameter offsets.
Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241861 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:20:37 +00:00
Matt Arsenault 0685a5c5ed AMDGPU/R600: Return correct chain when lowering loads
The other LowerLOAD should be returning the correct chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:47:03 +00:00
Mehdi Amini f29cc18dcb Make TargetLowering::getPointerTy() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11028

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241775 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:04 +00:00
Tom Stellard 953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00
Tom Stellard b1162b8d4b Revert "AMDGPU: Add core backend files for R600/SI codegen v6"
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:53 +00:00
Tom Stellard 23dc769a9b AMDGPU: Add core backend files for R600/SI codegen v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 14:17:08 +00:00