12125 Commits

Author SHA1 Message Date
NAKAMURA Takumi
09c0ea51ca Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248264 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:15:07 +00:00
NAKAMURA Takumi
c36e746e98 Reformat blank lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248263 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:14:39 +00:00
NAKAMURA Takumi
6902c8db26 Reformat comment lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248262 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:14:12 +00:00
NAKAMURA Takumi
d4cdf1962b Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248261 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:13:55 +00:00
Simon Pilgrim
de8d7c41ca [X86][SSE] Match zero/any extension shuffles that don't start from the first element
This patch generalizes the lowering of shuffles as zero extensions to allow extensions that don't start from the first element. It now recognises extensions starting anywhere in the lower 128-bits or at the start of any higher 128-bit lane.

The motivation was to reduce the number of high cost pshufb calls, but it also improves the SSE2 case as well.

Differential Revision: http://reviews.llvm.org/D12561


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248250 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 08:16:08 +00:00
Chad Rosier
c5d4530d42 [Machine Combiner] Refactor machine reassociation code to be target-independent.
No functional change intended.
Patch by Haicheng Wu <haicheng@codeaurora.org>!

http://reviews.llvm.org/D12887
PR24522

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248164 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 15:09:11 +00:00
Asaf Badouh
648a027c82 [X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FP
Differential Revision: http://reviews.llvm.org/D12524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248147 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 10:23:53 +00:00
Igor Breger
b0eb8fb69c AVX512: Implemented encoding and intrinsics for vcmpss/sd.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248121 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 15:15:10 +00:00
Asaf Badouh
fe11ff1d50 [X86][AVX512] extend support in Scalar conversion
add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics

Differential Revision: http://reviews.llvm.org/D12665

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248117 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 14:31:19 +00:00
Igor Breger
0d48c46954 AVX512: vsqrtss/sd encoding and intrinsics implementation.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248116 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 09:13:41 +00:00
Asaf Badouh
d3db2cf572 [X86][AVX512DQ] Add fpclass instruction
Differential Revision: http://reviews.llvm.org/D12931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248115 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 08:46:07 +00:00
Michael Kuperstein
5610c28853 [X86] Fix sitofp and uitofp instruction matching failures with long double and avx512
The operation action for i32 and i64 cannot be set to legal, as long double 
needs custom lowering.

Patch by: mitch.l.bodart@intel.com
Differential Revision: http://reviews.llvm.org/D12372


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248114 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 08:12:17 +00:00
Igor Breger
d425988995 AVX512: Implemented intrinsics for vshuff32x4, vshuff64x2, vshufi64x2, vshufi32x4
Added tests for intrinsics.

Differential Revision: http://reviews.llvm.org/D12525

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248113 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 07:18:53 +00:00
Igor Breger
28cce2ad25 AVX512: Implement instructions encoding, lowering and intrinsics
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.

Differential Revision: http://reviews.llvm.org/D11893

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248111 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 06:52:42 +00:00
Simon Pilgrim
afa71f40bf [X86][SSE] Vectorize CTTZ + CTTZ_ZERO_UNDEF
Now that we have fast vector CTPOP implementations we can use this to speed up vector CTTZ using the pattern (cttz(x) = ctpop((x & -x) - 1))

Additionally, for AVX512CD that provides lzcnt instructions we can use the pattern (cttz_undef(x) = (width - 1) - ctlz(x & -x))

Differential Revision: http://reviews.llvm.org/D12663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248091 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-19 13:22:57 +00:00
Reid Kleckner
f946dd0412 [WinEH] Make funclet return instrs pseudo instrs
This makes catchret look more like a branch, and less like a weird use
of BlockAddress. It also lets us get away from
llvm.x86.seh.restoreframe, which relies on the old parentfpoffset label
arithmetic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247936 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-17 20:43:47 +00:00
Elena Demikhovsky
2e5bf5535c AVX-512: shufflevector for i1 vectors <2 x i1> .. <64 x i1>
AVX-512 does not provide an instruction that shuffles mask register. So I do the following way:

mask-2-simd , shuffle simd , simd-2-mask

Differential Revision: http://reviews.llvm.org/D12727



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247876 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-17 06:53:12 +00:00
Eric Christopher
973f7aa32a constify the Function parameter to the TTI creation callback and
propagate to all callers/users/etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247864 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 23:38:13 +00:00
Reid Kleckner
436444d569 [WinEH] Rip out the landingpad-based C++ EH state numbering code
It never really worked, and the new code is working better every day.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247860 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 22:14:46 +00:00
Reid Kleckner
66ef931b43 [WinEH] Pull Adjectives and CatchObj out of the catchpad arg list
Clang now passes the adjectives as an argument to catchpad.

Getting the CatchObj working is simply a matter of threading another
static alloca through codegen, first as an alloca, then as a frame
index, and finally as a frame offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247844 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 20:16:27 +00:00
Reid Kleckner
1b86a3446f [WinEH] Skip state numbering when no EH pads are present
Otherwise we'd try to emit the thunk that passes the LSDA to
__CxxFrameHandler3. We don't emit the LSDA if there were no landingpads,
so we'd end up with an assembler error when trying to write the COFF
object.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247820 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 17:19:44 +00:00
Sanjay Patel
39490133e4 propagate fast-math-flags on DAG nodes
After D10403, we had FMF in the DAG but disabled by default. Nick reported no crashing errors after some stress testing, 
so I enabled them at r243687. However, Escha soon notified us of a bug not covered by any in-tree regression tests: 
if we don't propagate the flags, we may fail to CSE DAG nodes because differing FMF causes them to not match. There is
one test case in this patch to prove that point.

This patch hopes to fix or leave a 'TODO' for all of the in-tree places where we create nodes that are FMF-capable. I 
did this by putting an assert in SelectionDAG.getNode() to find any FMF-capable node that was being created without FMF
( D11807 ). I then ran all regression tests and test-suite and confirmed that everything passes.

This patch exposes remaining work to get DAG FMF to be fully functional: (1) add the flags to non-binary nodes such as
FCMP, FMA and FNEG; (2) add the flags to intrinsics; (3) use the flags as conditions for transforms rather than the
current global settings.

Differential Revision: http://reviews.llvm.org/D12095



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247815 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 16:31:21 +00:00
Michael Kuperstein
196a1036c4 [X86] Do not generate 64-bit pops of 32-bit GPRs.
When trying emit a stack adjustments using pops, frame lowering selects an
arbitrary free GPR. It should always select one from an appropriate class...
This fixes PR24649.

Patch by: amjad.aboud@intel.com
Differential Revision: http://reviews.llvm.org/D12609


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247785 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 11:27:20 +00:00
Michael Kuperstein
b82c32333b [X86] Fix emitEpilogue() to make less assumptions about pops
This is the mirror image of r242395.
When X86FrameLowering::emitEpilogue() looks for where to insert the %esp addition that
deallocates stack space used for local allocations, it assumes that any sequence of pop
instructions from function exit backwards consists purely of restoring callee-save registers.

This may be false, since from some point backward, the pops may be clean-up of stack space
allocated for arguments to a call.

Patch by: amjad.aboud@intel.com
Differential Revision: http://reviews.llvm.org/D12688


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247784 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 11:18:25 +00:00
Daniel Sanders
47b167dd84 Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Eric has replied and has demanded the patch be reverted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247702 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 16:17:27 +00:00
Daniel Sanders
9781f90c7e Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Summary:
This is the first patch in the series to migrate Triple's (which are ambiguous)
to TargetTuple's (which aren't).

For the moment, TargetTuple simply passes all requests to the Triple object it
holds. Once it has replaced Triple, it will start to implement the interface in
a more suitable way.

This change makes some changes to the public C++ API. In particular,
InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer()
now take TargetTuples instead of Triples. The other public C++ API's have
been left as-is for the moment to reduce patch size.

This commit also contains a trivial patch to clang to account for the C++ API
change. Thanks go to Pavel Labath for fixing LLDB for me.

Reviewers: rengolin

Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10969


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247692 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 14:08:28 +00:00
Daniel Sanders
a6aa0c3bcc Revert r247684 - Replace Triple with a new TargetTuple ...
LLDB needs to be updated in the same commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247686 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 13:46:21 +00:00
Daniel Sanders
7b82808e13 Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Summary:
This is the first patch in the series to migrate Triple's (which are ambiguous)
to TargetTuple's (which aren't).

For the moment, TargetTuple simply passes all requests to the Triple object it
holds. Once it has replaced Triple, it will start to implement the interface in
a more suitable way.

This change makes some changes to the public C++ API. In particular,
InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer()
now take TargetTuples instead of Triples. The other public C++ API's have
been left as-is for the moment to reduce patch size.

This commit also contains a trivial patch to clang to account for the C++ API
change.

Reviewers: rengolin

Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10969



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247683 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 13:17:40 +00:00
Daniel Sanders
c413998d28 Fix namespace indentation and missing blank lines before 'public:' in *MCAsmInfo.h. NFC.
This is to reduce noise in a following commit.

Also fixes a couple missing spaces before the reference operator.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247679 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 12:27:06 +00:00
Simon Pilgrim
29f50e9783 [X86][MMX] Added shuffle decodes for MMX/3DNow! shuffles.
Added shuffle decodes for MMX PUNPCK + PSHUFW shuffles.
Added shuffle decodes for 3DNow! PSWAPD shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247526 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-13 11:28:45 +00:00
Elena Demikhovsky
b21635658f AVX-512: Fixed a bug in OR/XOR operations for 512-bit FP values on KNL.
KNL does not have VXORPS, VORPS for 512-bit values.
I use integer VPXOR, VPOR that actually do the same.

X86ISD::FXOR/FOR are generated as a result of FSUB combining.

Differential Revision: http://reviews.llvm.org/D12753



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247523 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-13 08:15:15 +00:00
Sanjay Patel
d8fd22b7ec [x86] enable machine combiner reassociations for 128-bit vector logical integer insts (2nd try)
The changes in:
test/CodeGen/X86/machine-cp.ll
are just due to scheduling differences after some logic instructions were reassociated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247516 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-12 19:47:50 +00:00
Simon Pilgrim
b43332c8d1 [X86] Renamed lowerVectorShuffleAsUnpack NFCI.
Renamed to lowerVectorShuffleAsPermuteAndUnpack to make it clear that it lowers to more than just a UNPCK instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247513 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-12 18:26:47 +00:00
Simon Pilgrim
9114b92030 [X86] Moved lowerVectorShuffleWithUNPCK earlier to make reuse easier. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247511 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-12 16:03:06 +00:00
Sanjay Patel
69f08e598c revert r247506; need to verify changes in existing tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247507 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-12 15:27:31 +00:00
Sanjay Patel
e6c453bf2d [x86] enable machine combiner reassociations for 128-bit vector logical integer insts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247506 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-12 14:58:04 +00:00
Akira Hatanaka
8e2b613ef0 Use function attribute "stackrealign" to decide whether stack
realignment should be forced.

With this commit, we can now force stack realignment when doing LTO and
do so on a per-function basis. Also, add a new cl::opt option
"stackrealign" to CommandFlags.h which is used to force stack
realignment via llc's command line.

Out-of-tree projects currently using -force-align-stack to force stack
realignment should make changes to attach the attribute to the functions
in the IR.

Differential Revision: http://reviews.llvm.org/D11814


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247450 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-11 18:54:38 +00:00
Ahmed Bougacha
74869be273 [CodeGen] Refactor TLI/AtomicExpand interface to make LLSC explicit.
We used to have this magic "hasLoadLinkedStoreConditional()" callback,
which really meant two things:
- expand cmpxchg (to ll/sc).
- expand atomic loads using ll/sc (rather than cmpxchg).

Remove it, and, instead, introduce explicit callbacks:
- bool shouldExpandAtomicCmpXchgInIR(inst)
- AtomicExpansionKind shouldExpandAtomicLoadInIR(inst)

Differential Revision: http://reviews.llvm.org/D12557

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247429 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-11 17:08:28 +00:00
Ahmed Bougacha
f3d2de3832 [CodeGen] Rename AtomicRMWExpansionKind to AtomicExpansionKind.
This lets us generalize its usage to the other atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247428 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-11 17:08:17 +00:00
Reid Kleckner
3f3f976995 [WinEH] Push and pop EBP for 32-bit funclets
The Win32 EH runtime caller does not preserve EBP, even though it does
preserve the CSRs (EBX, ESI, EDI) for us. The result was that each
finally funclet call would leave the frame pointer off by 12 bytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247348 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 22:00:02 +00:00
Hans Wennborg
07a3b97f20 Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"
Except the changes that defined virtual destructors as =default, because that
ran into problems with GCC 4.7 and overriding methods that weren't noexcept.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247298 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 16:49:58 +00:00
Igor Breger
7744f3ca3f AVX512: Implemented encoding and intrinsics for
vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11802

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247276 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 12:54:54 +00:00
Hans Wennborg
2515069180 Revert r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"
This caused build breakges, e.g.
http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/24926

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247226 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 00:57:26 +00:00
Ahmed Bougacha
de3869437d [CodeGen] Make x86 nontemporal store patfrags generic. NFC.
To be used by other targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247225 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 00:53:15 +00:00
Reid Kleckner
75771885f8 [WinEH] Add codegen support for cleanuppad and cleanupret
All of the complexity is in cleanupret, and it mostly follows the same
codepaths as catchret, except it doesn't take a return value in RAX.

This small example now compiles and executes successfully on win32:
  extern "C" int printf(const char *, ...) noexcept;
  struct Dtor {
    ~Dtor() { printf("~Dtor\n"); }
  };
  void has_cleanup() {
    Dtor o;
    throw 42;
  }
  int main() {
    try {
      has_cleanup();
    } catch (int) {
      printf("caught it\n");
    }
  }

Don't try to put the cleanup in the same function as the catch, or Bad
Things will happen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247219 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 00:25:23 +00:00
Hans Wennborg
bfd007fd70 Fix Clang-tidy misc-use-override warnings, other minor fixes
Patch by Eugene Zelenko!

Differential Revision: http://reviews.llvm.org/D12740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247216 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-10 00:12:56 +00:00
Reid Kleckner
69d051c87d [SEH] Emit 32-bit SEH tables for the new EH IR
The 32-bit tables don't actually contain PC range data, so emitting them
is incredibly simple.

The 64-bit tables, on the other hand, use the same table for state
numbering as well as label ranges. This makes things more difficult, so
it will be implemented later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247192 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-09 21:10:03 +00:00
Renato Golin
792b67e240 Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding."
This reverts commit r247149, as it was breaking numerous buildbots of varied architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247177 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-09 19:44:40 +00:00
Matthias Braun
af5ff60200 Save LaneMask with livein registers
With subregister liveness enabled we can detect the case where only
parts of a register are live in, this is expressed as a 32bit lanemask.
The current code only keeps registers in the live-in list and therefore
enumerated all subregisters affected by the lanemask. This turned out to
be too conservative as the subregister may also cover additional parts
of the lanemask which are not live. Expressing a given lanemask by
enumerating a minimum set of subregisters is computationally expensive
so the best solution is to simply change the live-in list to store the
lanemasks as well. This will reduce memory usage for targets using
subregister liveness and slightly increase it for other targets

Differential Revision: http://reviews.llvm.org/D12442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247171 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-09 18:08:03 +00:00
Igor Breger
1676f595b1 AVX512: Implemented encoding and intrinsics for
vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11802

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247149 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-09 14:35:09 +00:00