Commit Graph

46851 Commits

Author SHA1 Message Date
Richard Smith
11110e1279 Increase tail dup threshold for -O3 from 3 to 4.
We see a modest performance improvement from this slightly higher tail dup threshold.

Differential Revision: https://reviews.llvm.org/D36775


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311139 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 23:38:41 +00:00
Craig Topper
1c92091839 [X86] Remove SSE/AVX patterns for AND/XOR/OR/ANDN that checked for the inputs being bitcasted from floating point types.
There's really no reason to do this we should just let isel pick the integer version and let the execution dependency fixing pass take care of moving to FP if necessary.

It's not very reliable to look for bitcasts at the edges of patterns. If for some reason one input was bitcasted and the other wasn't, or if one was a v4f32 bitcast and one was a v2f64 bitcast, we would have fallen back to the integer pattern anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311138 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 23:20:57 +00:00
Tim Northover
e8fd209647 GlobalISel (AArch64): fix ABI at border between GPRs and SP.
If a struct would end up half in GPRs and half on SP the ABI says it should
actually go entirely on the stack. We were getting this wrong in GlobalISel
before, causing compatibility issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311137 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 23:14:01 +00:00
Geoff Berry
d93db263e5 Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
Two issues identified by buildbots were addressed:
    - The pass no longer forwards COPYs to physical register uses, since
      doing so can break code that implicitly relies on the physical
      register number of the use.
    - The pass no longer forwards COPYs to undef uses, since doing so
      can break the machine verifier by creating LiveRanges that don't
      end on a use (since the undef operand is not considered a use).

    [MachineCopyPropagation] Extend pass to do COPY source forwarding

    This change extends MachineCopyPropagation to do COPY source forwarding.

    This change also extends the MachineCopyPropagation pass to be able to
    be run during register allocation, after physical registers have been
    assigned, but before the virtual registers have been re-written, which
    allows it to remove virtual register COPY LiveIntervals that become dead
    through the forwarding of all of their uses.

    Reviewers: qcolombet, javed.absar, MatzeB, jonpa

    Subscribers: jyknight, nemanjai, llvm-commits, nhaehnle, mcrosier, mgorny

    Differential Revision: https://reviews.llvm.org/D30751

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311135 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 23:06:55 +00:00
Jonas Devlieghere
84dc1f35b1 Revert "[Debug info] Transfer DI to fragment expressions for split integer values."
This reverts commit r311102.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311111 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 17:58:33 +00:00
Alexey Bataev
752c0a0190 [SimplifyCFG] Add a test for preserve store alignment, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311106 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 17:26:52 +00:00
Sanjay Patel
6257fc9a0b [x86] add tests for vector select-of-constants; NFC
We've discussed canonicalizing to this form in IR, so the backend
should be prepared to lower these in ways better than what we see
here in most cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311103 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 17:07:37 +00:00
Jonas Devlieghere
6c37616078 [Debug info] Transfer DI to fragment expressions for split integer values.
This patch teaches the SDag type legalizer how to split up debug info for
integer values that are split into a hi and lo part.

Differential Revision: https://reviews.llvm.org/D36805



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311102 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 17:06:48 +00:00
Sanjay Patel
36dc99ec47 [PowerPC] add tests for vector select-of-constants; NFC
We've discussed canonicalizing to this form in IR, so the backend
should be prepared to lower these in ways better than what we see
here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311099 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 17:03:11 +00:00
Adrian Prantl
cb8c418e34 Improve line debug info when translating a CaseBlock to SDNodes.
The SelectionDAGBuilder translates various conditional branches into
CaseBlocks which are then translated into SDNodes. If a conditional
branch results in multiple CaseBlocks only the first CaseBlock is
translated into SDNodes immediately, the rest of the CaseBlocks are
put in a queue and processed when all LLVM IR instructions in the
basic block have been processed.

When a CaseBlock is transformed into SDNodes the SelectionDAGBuilder
is queried for the current LLVM IR instruction and the resulting
SDNodes are annotated with the debug info of the current
instruction (if it exists and has debug metadata).

When the deferred CaseBlocks are processed, the SelectionDAGBuilder
does not have a current LLVM IR instruction, and the resulting SDNodes
will not have any debuginfo. As DwarfDebug::beginInstruction() outputs
a .loc directive for the first instruction in a labeled
block (typically the case for something coming from a CaseBlock) this
tends to produce a line-0 directive.

This patch changes the handling of CaseBlocks to store the current
instruction's debug info into the CaseBlock when it is created (and the
SelectionDAGBuilder knows the current instruction) and to always use
the stored debug info when translating a CaseBlock to SDNodes.

Patch by Frej Drejhammar!

Differential Revision: https://reviews.llvm.org/D36671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311097 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 16:57:13 +00:00
Craig Topper
7feb6fc8e5 [AVX512] Don't switch unmasked subvector insert/extract instructions when AVX512DQI is enabled.
There's no reason to switch instructions with and without DQI. It just creates extra isel patterns and test divergences.

There is however value in enabling the masked version of the instructions with DQI.

This required introducing some new multiclasses to enabling this splitting.

Differential Revision: https://reviews.llvm.org/D36661

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311091 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 15:40:25 +00:00
Victor Leschuk
7f37f07d7b Mark Verifier/invalid-eh.ll as unsupported on windows
Mark this unsupported for now as it causes tests hangs on buildbot.
Will place it back when the problem is debugged.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311089 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 15:07:03 +00:00
Simon Dardis
987e30d867 [dfsan] Add explicit zero extensions for shadow parameters in function wrappers.
In the case where dfsan provides a custom wrapper for a function,
shadow parameters are added for each parameter of the function.
These parameters are i16s. For targets which do not consider this
a legal type, the lack of sign extension information would cause
LLVM to generate anyexts around their usage with phi variables
and calling convention logic.

Address this by introducing zero exts for each shadow parameter.

Reviewers: pcc, slthakur

Differential Revision: https://reviews.llvm.org/D33349


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311087 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 14:14:25 +00:00
Daniel Sanders
c3fa9e8b81 [globalisel][tablegen] Generate TypeObject table. NFC
Summary:
Generate the type table from the types used by a target rather than hard-coding
the union of types used by all targets.

Depends on D36084

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: rovka

Subscribers: kristof.beyls, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D36085

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311084 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 13:18:35 +00:00
Simon Pilgrim
8f5ac0464c [DAGCombiner] Add support for non-uniform constant vectors to (mul x, (1 << c)) -> x << c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311083 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 13:03:34 +00:00
Davide Italiano
75aa840968 [Verifier] Avoid visiting DIGlobalVariables twice.
We currently visit them twice.
Once, through `visitMDNode()` -> (the code generated by)
  `../include/llvm/IR/Metadata.def:109` -> `visitDIGlobalVariable()`
Then, through `visitMDNode()` -> `visitDIGlobalVariableExpression()`
  -> `visitDIGlobalVariable()`

This results in verification failures printed twice, e.g.:

  $ ./opt -verify ../../test/DebugInfo/pr34186.ll
  missing global variable type
  !4 = distinct !DIGlobalVariable(name: "pat", scope: !0,
    file: !1, line: 27, isLocal: true, isDefinition: true)
  missing global variable type
  !4 = distinct !DIGlobalVariable(name: "pat", scope: !0,
    file: !1, line: 27, isLocal: true, isDefinition: true)
  ./opt: ../../test/DebugInfo/pr34186.ll: error: input module is broken!

The patch removes one call so we ensure each GV is visited exactly once.

Differential Revision:  https://reviews.llvm.org/D36797

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311081 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 11:32:21 +00:00
Ayal Zaks
cd8f8f7fd4 [LV] Using VPlan to model the vectorized code and drive its transformation
VPlan is an ongoing effort to refactor and extend the Loop Vectorizer. This
patch introduces the VPlan model into LV and uses it to represent the vectorized
code and drive the generation of vectorized IR.

In this patch VPlan models the vectorized loop body: the vectorized control-flow
is represented using VPlan's Hierarchical CFG, with predication refactored from
being a post-vectorization-step into a vectorization planning step modeling
if-then VPRegionBlocks, and generating code inline with non-predicated code. The
vectorized code within each VPBasicBlock is represented as a sequence of
Recipes, each responsible for modelling and generating a sequence of IR
instructions. To keep the size of this commit manageable the Recipes in this
patch are coarse-grained and capture large chunks of LV's code-generation logic.
The constructed VPlans are dumped in dot format under -debug.

This commit retains current vectorizer output, except for minor instruction
reorderings; see associated modifications to lit tests.

For further details on the VPlan model see docs/Proposals/VectorizationPlan.rst
and its references.

Authors: Gil Rapaport and Ayal Zaks

Differential Revision: https://reviews.llvm.org/D32871


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311077 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 09:29:59 +00:00
Daniel Sanders
2cd3b1f607 Re-commit: [globalisel][tablegen] Support zero-instruction emission.
Summary:
Support the case where an operand of a pattern is also the whole of the
result pattern. In this case the original result and all its uses must be
replaced by the operand. However, register class restrictions can require
a COPY. This patch handles both cases by always emitting the copy and
leaving it for the register allocator to optimize.

The previous commit failed on Windows machines due to a flaw in the sort
predicate which allowed both A < B < C and B == C to be satisfied
simultaneously. The cause of this was some sloppiness in the priority order of
G_CONSTANT instructions compared to other instructions. These had equal priority
because it makes no difference, however there were operands had higher priority
than G_CONSTANT but lower priority than any other instruction. As a result, a
priority order between G_CONSTANT and other instructions must be enforced to
ensure the predicate defines a strict weak order.

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D36084


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311076 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 09:26:14 +00:00
Jonas Paulsson
59bdb88371 [SystemZ, MachineScheduler] Improve post-RA scheduling.
The idea of this patch is to continue the scheduler state over an MBB boundary
in the case where the successor block has only one predecessor. This means
that the scheduler will continue in the successor block (after emitting any
branch instructions) with e.g. maintained processor resource counters.
Benchmarks have been confirmed to benefit from this.

The algorithm in MachineScheduler.cpp that extracts scheduling regions of an
MBB has been extended so that the strategy may optionally reverse the order
of processing the regions themselves. This is controlled by a new method
doMBBSchedRegionsTopDown(), which defaults to false.

Handling the top-most region of an MBB first also means that a top-down
scheduler can continue the scheduler state across any scheduling boundary
between to regions inside MBB.

Review: Ulrich Weigand, Matthias Braun, Andy Trick.
https://reviews.llvm.org/D35053

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311072 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 08:33:44 +00:00
Elad Cohen
605e60b1d2 [SelectionDAG] Teach the vector-types operand scalarizer about SETCC
When v1i1 is legal (e.g. AVX512) the legalizer can reach
a case where a v1i1 SETCC with an illgeal vector type operand
wasn't scalarized (since v1i1 is legal) but its operands does
have to be scalarized. This used to assert because SETCC was
missing from the vector operand scalarizer.

This patch attemps to teach the legalizer to handle these cases
by scalazring the operands, converting the node into a scalar
SETCC node.

Differential revision: https://reviews.llvm.org/D36651

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311071 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 08:06:36 +00:00
Serguei Katkov
a01b42e49a [CGP] Fix the rematerialization of gc.relocates
If we want to substitute the relocation of derived pointer with gep of base then
we must ensure that relocation of base dominates the relocation of derived pointer.

Currently only check for basic block is present. However it is possible that both
relocation are in the same basic block but relocation of derived pointer is defined
earlier.

The patch moves the relocation of base pointer right before relocation of derived
pointer in this case.

Reviewers: sanjoy,artagnon,igor-laevsky,reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36462


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311067 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 05:48:30 +00:00
Geoff Berry
a6a5be21df Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
This reverts commit r311038.

Several buildbots are breaking, and at least one appears to be due to
the forwarding of physical regs enabled by this change.  Reverting while
I investigate further.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311062 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 04:04:11 +00:00
Saleem Abdulrasool
e042428b3e ARM: mark CPSR as clobbered for Windows VLAs
When lowering a VLA, we emit a __chstk call.  However, this call can
internally clobber CPSR.  We did not mark this register as an ImpDef,
which could potentially allow a comparison to be hoisted above the call
to `__chkstk`.  In such a case, the CPSR could be clobbered, and the
check invalidated.  When the support was initially added, it seemed that
the call would take care of preventing CPSR from being clobbered, but
this is not the case.  Mark the register as clobbered to fix a possible
state corruption.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311061 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 02:42:24 +00:00
Jakub Kuderski
85bef5a5c4 Reapply: [ADCE][Dominators] Teach ADCE to preserve dominators
Summary:
This patch teaches ADCE to preserve both DominatorTrees and PostDominatorTrees.

I didn't notice any performance impact when bootstrapping clang with this patch.

The patch was originally committed in r311039 and reverted in r311049.
This revision fixes the problem with not adding a dependency on the
DominatorTreeWrapperPass for the LegacyPassManager.

Reviewers: dberlin, chandlerc, sanjoy, davide, grosser, brzycki

Reviewed By: davide

Subscribers: grandinj, zhendongsu, llvm-commits, david2050

Differential Revision: https://reviews.llvm.org/D35869

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311057 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-17 01:41:49 +00:00
Sanjay Patel
4480e9fa9b [x86] add cmov promotion tests for D36711; NFC
This way we can see what the current codegen looks like.
I've also explicitly added/removed the cmov attribute from the RUN lines,
so we know exactly what we're checking in the runs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311052 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 22:50:11 +00:00
Amjad Aboud
58903453c3 [InstCombine] Teach canEvaluateTruncated to handle arithmetic shift (including those with vector splat shift amount)
Differential Revision: https://reviews.llvm.org/D36784


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311050 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 22:42:38 +00:00
Jakub Kuderski
7d9adf9346 Revert "[ADCE][Dominators] Teach ADCE to preserve dominators"
This reverts commit r311039. The patch caused the
`test/Bindings/OCaml/Output/scalar_opts.ml` to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311049 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 22:10:53 +00:00
Craig Topper
454718f93b [InstCombine] Make folding (X >s -1) ? C1 : C2 --> ((X >>s 31) & (C2 - C1)) + C1 support splat vectors
This also uses decomposeBitTestICmp to decode the compare.

Differential Revision: https://reviews.llvm.org/D36781

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311044 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 21:52:07 +00:00
Jakub Kuderski
56c786ccab [ADCE][Dominators] Teach ADCE to preserve dominators
Summary:
This patch teaches ADCE to preserve both DominatorTrees and PostDominatorTrees.

I didn't notice any performance impact when bootstrapping clang with this patch.

Reviewers: dberlin, chandlerc, sanjoy, davide, grosser, brzycki

Reviewed By: davide

Subscribers: grandinj, zhendongsu, llvm-commits, david2050

Differential Revision: https://reviews.llvm.org/D35869

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311039 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 20:50:23 +00:00
Geoff Berry
31db6f3bd2 [MachineCopyPropagation] Extend pass to do COPY source forwarding
This change extends MachineCopyPropagation to do COPY source forwarding.

This change also extends the MachineCopyPropagation pass to be able to
be run during register allocation, after physical registers have been
assigned, but before the virtual registers have been re-written, which
allows it to remove virtual register COPY LiveIntervals that become dead
through the forwarding of all of their uses.

Reviewers: qcolombet, javed.absar, MatzeB, jonpa

Subscribers: jyknight, nemanjai, llvm-commits, nhaehnle, mcrosier, mgorny

Differential Revision: https://reviews.llvm.org/D30751

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311038 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 20:50:01 +00:00
Simon Atanasyan
10781fc2c1 [mips] Handle R_MIPS_TLS_DTPREL32/64 relocations in the RelocVisitor
Debug information for TLS variables on MIPS might have R_MIPS_TLS_DTPREL32
or R_MIPS_TLS_DTPREL64 relocations. This patch adds a support for such
relocations in the `RelocVisitor`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311031 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 19:01:22 +00:00
Xinliang David Li
2f4468d845 [PGO] Fix ThinLTO crash
Differential Revsion: http://reviews.llvm.org/D36640


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311023 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 17:18:01 +00:00
Simon Pilgrim
43d9a37996 [X86] Regenerate immediate store merging tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311016 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 16:22:19 +00:00
Hal Finkel
a62eb7baad [BDCE] Don't check demanded bits on unsized types
To clear assumptions that are potentially invalid after trivialization, we need
to walk the use/def chain. Normally, the only way to reach an instruction with
an unsized type is via an instruction that has side effects (or otherwise will
demand its input bits). That would stop the walk. However, if we have a
readnone function that returns an unsized type (e.g., void), we must avoid
asking for the demanded bits of the function call's return value. A
void-returning readnone function is always dead (and so we can stop walking the
use/def chain here), but the check is necessary to avoid asserting.

Fixes PR34211.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311014 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 16:09:22 +00:00
Davide Italiano
c79eba5730 [Verifier] Reject globals without a type associated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311012 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 15:16:33 +00:00
Dmitry Preobrazhensky
917eb1c735 [AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16
This change implements features postponed in https://reviews.llvm.org/D35424 because of a dependency on https://reviews.llvm.org/D36322

Reviewers: SamWot, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D36694

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311011 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 15:16:32 +00:00
Balaram Makam
edd00a7e54 Revert "MachineInstr: Reason locally about some memory objects before going to AA."
r310825 caused the clang-ppc64le-linux-lnt bot to go red
(http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/5712)
because of a test-suite failure of
SingleSource/UnitTests/2003-07-09-SignedArgs

This reverts commit 0028f6a872.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311008 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 14:17:43 +00:00
Dmitry Preobrazhensky
600899c871 [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes
See Bug 34152: https://bugs.llvm.org//show_bug.cgi?id=34152

Reviewers: SamWot, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D36674

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311006 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 13:51:56 +00:00
Simon Pilgrim
b148872e50 [CostModel][X86][XOP] Improve costs for XOP shuffles
VPPERM/VPERMIL2PD/VPERMIL2PS all provide more effective 2-input shuffles than regular AVX instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311005 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 13:50:20 +00:00
Davide Italiano
9c770381b9 [DI] Every DIGlobalVariable should have a type.
I'll make this a verifier check to catch other violations. This
commit fixes the tests already in tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311004 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 13:39:07 +00:00
Simon Dardis
c29af95cf1 [mips] Handle variables with an explicit section and interactions with .sdata, .sbss
If a variable has an explicit section such as .sdata or .sbss, it is placed
in that section and accessed in a gp relative manner. This overrides the global
-G setting.

Otherwise if a variable has a explicit section attached to it, such as '.rodata'
or '.mysection', it is not placed in the small data section. This also overrides
the global -G setting.

Reviewers: atanasyan, nitesh.jain

Differential Revision: https://reviews.llvm.org/D36616


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311001 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 12:18:04 +00:00
Sam Parker
f281371190 [ARM] Improve loop unrolling for Cortex-M
- Set the default runtime unroll count to 4 and use the newly added
  UnrollRemainder option.
- Create loop cost and force unroll for a cost less than 12.
- Disable unrolling on Thumb1 only targets.

Differential Revision: https://reviews.llvm.org/D36134


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310997 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 07:42:44 +00:00
Igor Breger
2d6d71c7e1 [GlobalISel][X86] Fix mir tests, use correct physical register.NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310996 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 07:25:51 +00:00
Martin Storsjo
4c13451fc9 [llvm-dlltool] Fix creating stdcall/fastcall import libraries for i386
Hook up the -k option (that in the original GNU dlltool removes the
@n suffix from the symbol that the final executable ends up linked to).

In llvm-dlltool, make sure that functions end up with the undecorate
name type if this option is set and they are decorated. In mingw, when
creating import libraries from def files instead of creating an import
library as a side effect of linking a DLL, the symbol names in the def
contain the stdcall/fastcall decoration (but no leading underscore).

By setting the undecorate name type, a linker linking to the import
library will omit the decoration from the DLL import entry.

With this in place, mingw-w64 for i386 built with llvm-dlltool/clang
produces import libraries that actually work.

Differential Revision: https://reviews.llvm.org/D36548

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310990 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 05:18:36 +00:00
Stanislav Mekhanoshin
2df3fafbea [AMDGPU] Eliminate no effect instructions before s_endpgm
Differential Revision: https://reviews.llvm.org/D36585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310987 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 04:43:49 +00:00
Dehao Chen
e5914dd1a3 Merge debug info when hoist then-else code to if.
Summary: When we move then-else code to if, we need to merge its debug info, otherwise the hoisted instruction may have inaccurate debug info attached.

Reviewers: aprantl, probinson, dblaikie, echristo, loladiro

Reviewed By: aprantl

Subscribers: sanjoy, llvm-commits

Differential Revision: https://reviews.llvm.org/D36778

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310985 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 01:55:26 +00:00
Derek Schuff
9689681e1b [WebAssembly] Remove infinite loop from reg-stackify test
r310940 exposed reverse-unreachable code to some optimizers,
which caused some of the code in this test to be sunk, changing
the input to the pass and breaking the exptectations.

Since that change is irrelevant to this particular test, this change
just adds an exit node to work around the problem; the
test should really be more robust (or be an MIR test?) but this preserves
the existing test intent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310981 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 00:49:44 +00:00
Quentin Colombet
156a10346f [VirtRegRewriter] Properly model the register liveness on undef subreg definition
Undef subreg definition means that the content of the super register
doesn't matter at this point. While that's true for virtual registers,
this may not hold when replacing them with actual physical registers.
Indeed, some part of the physical register may be coalesced with the
related virtual register and thus, the values for those parts matter and
must be live.

The fix consists in checking whether or not subregs of the physical register
being assigned to an undef subreg definition are live through that def and
insert an implicit use if they are. Doing so, will keep them alive until
that point like they should be.

E.g., let vreg14 being assigned to R0_R1 then
%vreg14:gsub_0<def,read-undef> = COPY %R0 ; <-- R1 is still live here
%vreg14:gsub_1<def> = COPY %R1

Before this changes, the rewriter would change the code into:
%R0<def> = KILL %R0, %R0_R1<imp-def> ; <-- this tells R1 is redefined
%R1<def> = KILL %R1, %R0_R1<imp-def>, %R0_R1<imp-use> ; this value of this R1
                                                      ; is believed to come
                                                      ; from the previous
                                                      ; instruction

Because of this invalid liveness, later pass could make wrong choices and in
particular clobber live register as it happened with the register scavenger in
llvm.org/PR34107

Now we would generate:
%R0<def> = KILL %R0, %R0_R1<imp-def>, %R0_R1<imp-use> ; This tells R1 needs to
                                                      ; reach this point
%R1<def> = KILL %R1, %R0_R1<imp-def>, %R0_R1<imp-use>

The bug has been here forever, it got exposed recently because the register
scavenger got smarter.

Fixes llvm.org/PR34107

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310979 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-16 00:17:05 +00:00
Kuba Mracek
d7e9f19e45 Revert archive-* tests from r310953, there were test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310974 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-15 23:41:34 +00:00
Craig Topper
30908807b6 [InstCombine] Teach canEvaluateZExtd and canEvaluateTruncated to handle vector shifts with splat shift amount
We were only allowing ConstantInt before. This patch allows splat of ConstantInt too.

Differential Revision: https://reviews.llvm.org/D36763

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310970 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-15 22:48:41 +00:00