Commit Graph

63887 Commits

Author SHA1 Message Date
Aaron Watry
546dcc5ddc R600: Add support for LDS atomic subtract
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190200 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 20:17:42 +00:00
Manman Ren
e42279cda4 Debug Info: Use identifier to reference DIType in containing type field of
a DICompositeType.
    
Verifier is updated accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 18:46:00 +00:00
Manman Ren
5930eabe0f Debug Info: Move a helper function getTypeIdentifier from DIBuilder to be part
of DIType.
    
Implement DIType::generateRef to return a type reference. This function will be
used in setContaintingType and in DIBuilder to generete the type reference.
    
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190188 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 18:27:00 +00:00
Andrew Trick
fb386db636 mi-sched: cleanup register pressure update, remove a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 17:32:47 +00:00
Andrew Trick
6bf0c6c535 mi-sched: improve regpressure tracing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 17:32:44 +00:00
Andrew Trick
fd30312c49 mi-sched: print tree size in -view-misched-dags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190179 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 17:32:42 +00:00
Andrew Trick
1251bcccc1 mi-sched: register pressure update tracing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190178 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 17:32:39 +00:00
Andrew Trick
f9c2fa8341 mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.
The latency based scheduling could induce spills in some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190177 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 17:32:36 +00:00
Andrew Trick
38e61122f2 Added MachineSchedPolicy.
Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 17:32:34 +00:00
Matthias Braun
b63db85350 avoid unnecessary direct access to LiveInterval::ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 16:44:32 +00:00
Matthias Braun
1920156982 remove unused argument from LiveRanges::join()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 16:44:29 +00:00
Matthias Braun
2d5558cbae remove pointless assert
The if above it ensures the property anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190168 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 16:44:27 +00:00
Matthias Braun
c725865bbc fix comment
There's no 'B3' in the example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190167 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 16:44:25 +00:00
Daniel Sanders
a86062c4b1 [mips][msa] Indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 13:25:06 +00:00
Daniel Sanders
5cb39b22fb [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190155 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 13:15:05 +00:00
Vladimir Medic
638382e6f1 This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 13:08:00 +00:00
Daniel Sanders
3aaa3e31aa [mips][msa] Made the operand register sets optional for the VEC formats
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190153 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 13:01:47 +00:00
Vladimir Medic
dadd1fba32 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:53:21 +00:00
Daniel Sanders
9e935a77a5 [mips][msa] Made the operand register sets optional for the ELM_INSVE formats
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:50:52 +00:00
Daniel Sanders
b9987d1aa1 [mips][msa] Made the operand register sets optional for the 3RF_4RF format
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190150 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:44:13 +00:00
Vladimir Medic
bf7f7b5e0e This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:41:17 +00:00
Tim Northover
a5eeb9da05 SelectionDAG: create correct BooleanContent constants
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:38:12 +00:00
Daniel Sanders
888497d8a2 [mips][msa] Made the operand register sets optional for the 3RF formats
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190146 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:32:57 +00:00
Daniel Sanders
6976d75415 [mips][msa] Made the operand register sets optional for the 3R_4R format
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:30:43 +00:00
Vladimir Medic
a674463aac This patch adds support for microMIPS disassembler and disassembler make check tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:30:36 +00:00
Daniel Sanders
99d02d1325 [mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:28:13 +00:00
Daniel Sanders
d31c238372 [mips][msa] Made the operand register sets optional for the I8 format
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190142 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:25:47 +00:00
Daniel Sanders
7d3da67611 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:23:19 +00:00
Daniel Sanders
bfb9bab243 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190140 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:10:24 +00:00
Richard Sandiford
aff1c6427c [SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 11:51:39 +00:00
Daniel Sanders
e3273b3275 [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 11:01:38 +00:00
Daniel Sanders
cc538affd2 [mips][msa] Made the operand register sets optional for the 3R format
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 10:59:24 +00:00
Daniel Sanders
3f1acd55a8 [mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 10:55:15 +00:00
Richard Sandiford
867f9501f6 [SystemZ] Use XC for a memset of 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 10:25:07 +00:00
Matt Arsenault
4598bd53ab Use type helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190113 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 00:37:24 +00:00
Matt Arsenault
ce8e4647bf Teach CodeGenPrepare about address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 00:18:43 +00:00
Tom Stellard
c3b5c042a4 R600: Coding style
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190110 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 23:55:13 +00:00
Juergen Ributzka
d7174719a9 [X86] Perform VSELECT DAG combines also before DAG type legalization.
If the DAG already has only legal types, then the second round of DAG combines
is skipped. In this case VSELECT+SETCC patterns that match a more efficient
instruction (e.g. min/max) are never recognized.

This fix allows VSELECT+SETCC combines if the types are already legal before DAG
type legalization.

Reviewer: Nadav

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 23:02:56 +00:00
Kevin Enderby
d8e2f1757d Fixed a crash in the integrated assembler for Mach-O when a symbol difference
expression uses an assembler temporary symbol from an assignment.  In this case
the symbol does not have a fragment so the use of getFragment() would be NULL
and caused a crash. In the case of an assembler temporary symbol we want to use
the AliasedSymbol (if any) which will create a local relocation entry, but if
it is not an assembler temporary symbol then let it use that symbol with an
external relocation entry.

rdar://9356266


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 20:25:06 +00:00
Matt Arsenault
596aa123f4 Consistently use dbgs() in debug printing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 19:48:28 +00:00
Matt Arsenault
3987e532f7 R600: Fix i64 to i32 trunc on SI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 19:41:10 +00:00
Rafael Espindola
466fa17aba Remove unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 19:15:21 +00:00
Yunzhong Gao
ed119820f2 Improve handling of .file, .include and .incbin directives to
allow escaped octal character sequences.

The patch was discussed in Phabricator. See:
http://llvm-reviews.chandlerc.com/D1289



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190089 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 19:14:26 +00:00
Manman Ren
bc66071baa Debug Info: Use identifier to reference DIType in base type field of
ptr_to_member.

We introduce a new class DITypeRef that represents a reference to a DIType.
It wraps around a Value*, which can be either an identifier in MDString
or an actual MDNode. The class has a helper function "resolve" that
finds the actual MDNode for a given DITypeRef.

We specialize getFieldAs to return a field that is a reference to a
DIType. To correctly access the base type field of ptr_to_member,
getClassType now calls getFieldAs<DITypeRef> to return a DITypeRef.

Also add a typedef for DITypeIdentifierMap and a helper
generateDITypeIdentifierMap in DebugInfo.h. In DwarfDebug.cpp, we keep
a DITypeIdentifierMap and call generateDITypeIdentifierMap to actually
populate the map.

Verifier is updated accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190081 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 18:48:31 +00:00
Tom Stellard
79916948e1 R600: Add support for local memory atomic add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190080 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 18:38:09 +00:00
Tom Stellard
756f382ac1 R600: Expand SELECT nodes rather than custom lowering them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190079 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 18:38:03 +00:00
Tom Stellard
470c451574 R600: Fix incorrect LDS size calculation
GlobalAdderss nodes that appeared in more than one basic block were
being counted twice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 18:37:57 +00:00
Tom Stellard
402b8e2175 R600/SI: Don't emit S_WQM_B64 instruction for compute shaders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190077 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 18:37:52 +00:00
Tom Stellard
791cdd5fe0 R600: Fix segfault in R600TextureIntrinsicReplacer
This pass was segfaulting when it ran into a non-intrinsic function
call.  Function calls are not supported, so now instead of segfaulting,
we will get an assertion failure with a nice error message.

I'm not sure how to test this using lit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190076 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 18:37:45 +00:00
Eric Christopher
577056f89c Move accelerator table defines and constants to Dwarf.h since
we're proposing it for DWARF5.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 18:20:16 +00:00