1237 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
1b5d21e1e4 [Hexagon] Handle instruction latency for 0 or 2 cycles
The Hexagon schedulers need to handle instructions with a latency
of 0 or 2 more accurately. The problem, in v60, is that a dependence
between two instructions with a 2 cycle latency can use a .cur version
of the source to achieve a 0 cycle latency when the use is in the
same packet. Any othe use, must be at least 2 packets later, or a
stall occurs. In other words, the compiler does not want to schedule
the dependent instructions 1 cycle later.

To achieve this, the latency adjustment code allows only a single
dependence to have a zero latency. All other instructions have the
other value, which is typically 2 cycles. We use a heuristic to
determine which instruction gets the 0 latency.

The Hexagon machine scheduler was also changed to increase the cost
associated with 0 latency dependences than can be scheduled in the
same packet.

Patch by Brendon Cahoon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275625 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 21:34:02 +00:00
Krzysztof Parzyszek
866d448f64 [Hexagon] Make MI scheduler check for stalls in previous packet on v60
Patch by Ikhlas Ajbar.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275606 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 20:16:03 +00:00
Krzysztof Parzyszek
d5ecd00014 [Hexagon] Replace postprocessDAG with a more elaborate DAG mutation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275598 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 19:09:37 +00:00
Justin Lebar
b2d6ad7cfd [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends.
Summary:
Instead, we take a single flags arg (a bitset).

Also add a default 0 alignment, and change the order of arguments so the
alignment comes before the flags.

This greatly simplifies many callsites, and fixes a bug in
AMDGPUISelLowering, wherein the order of the args to getLoad was
inverted.  It also greatly simplifies the process of adding another flag
to getLoad.

Reviewers: chandlerc, tstellarAMD

Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits

Differential Revision: http://reviews.llvm.org/D22249

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275592 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 18:27:10 +00:00
Justin Lebar
14fc45e102 [CodeGen] Take a MachineMemOperand::Flags in MachineFunction::getMachineMemOperand.
Summary:
Previously we took an unsigned.

Hooray for type-safety.

Reviewers: chandlerc

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D22282

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275591 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 18:26:59 +00:00
Krzysztof Parzyszek
5e3461ebc2 [Hexagon] Add a scheduling DAG mutation
- Remove output dependencies on USR_OVF register.
- Update chain edge latencies between v60 vector loads/stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275586 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 17:48:09 +00:00
Krzysztof Parzyszek
bd8bfbd4cb [Hexagon] Update instruction itineraries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275578 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 16:58:34 +00:00
Krzysztof Parzyszek
76ebffffd3 [Hexagon] Fixes/changes to instruction selection
- Add patterns for rr/abs addressing modes.
- Set addrMode to PostInc where necessary.
- Misc fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275574 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 16:29:02 +00:00
Krzysztof Parzyszek
733cec8f05 [Hexagon] Improve patterns with stack-based addressing
- Treat bitwise OR with a frame index as an ADD wherever possible, fold it
  into addressing mode.
- Extend patterns for memops to allow memops with frame indexes as address
  operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275569 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 15:35:52 +00:00
Jacques Pienaar
48ed4ab2d6 Rename AnalyzeBranch* to analyzeBranch*.
Summary: NFC. Rename AnalyzeBranch/AnalyzeBranchPredicate to analyzeBranch/analyzeBranchPredicate to follow LLVM coding style and be consistent with TargetInstrInfo's analyzeCompare and analyzeSelect.

Reviewers: tstellarAMD, mcrosier

Subscribers: mcrosier, jholewinski, jfb, arsenm, dschuff, jyknight, dsanders, nemanjai

Differential Revision: https://reviews.llvm.org/D22409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275564 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-15 14:41:04 +00:00
Krzysztof Parzyszek
1a360b3be9 [Hexagon] Packetize function call arguments with tail call instructions
On Hexagon is it legal to packetize the instructions setting up call
arguments with the call instruction itself. This was already done,
except for tail calls. Make sure tail calls are handled as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275458 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-14 19:30:55 +00:00
Duncan P. N. Exon Smith
8c13ec21d3 Hexagon: Avoid implicit iterator conversions, NFC
Avoid implicit iterator conversions from MachineInstrBundleIterator to
MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr&
over MachineInstr* and switching to range-based for loops.

There's a long tail of API cleanup here, but I'm planning to leave the
rest to the Hexagon maintainers.  HexagonInstrInfo defines many of its
own predicates, and most of them still take MachineInstr*.  Some of
those actually check for nullptr, so I didn't feel comfortable changing
them to MachineInstr& en masse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275142 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-12 01:55:32 +00:00
Nirav Dave
6b00c9f9a9 Fix branch relaxation in 16-bit mode.
Thread through MCSubtargetInfo to relaxInstruction function allowing relaxation
to generate jumps with 16-bit sized immediates in 16-bit mode.

This fixes PR22097.

Reviewers: dwmw2, tstellarAMD, craig.topper, jyknight

Subscribers: jfb, arsenm, jyknight, llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D20830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275068 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-11 14:23:53 +00:00
Duncan P. N. Exon Smith
04671b92e9 Target: Avoid getFirstTerminator() => pointer, NFC
Stop using an implicit conversion from the return of
MachineBasicBlock::getFirstTerminator to MachineInstr*.  In two cases,
directly dereference to a MachineInstr& since later code assumes it's
valid.  In a third case, change to an iterator since later code checks
against MachineBasicBlock::end.

Although the fix for the third case avoids undefined behaviour, I expect
this doesn't cause a functionality change in practice (since the basic
block already has a terminator).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274898 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 18:26:20 +00:00
Benjamin Kramer
b4e53350f9 [Hexagon] Create global std::map lazily.
This could of course be a simple binary search with no global state
involved at all if someone cares enough. Just don't make everyone
linking the hexagon backend pay for it on process startup and shutdown.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274437 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-02 13:05:12 +00:00
Krzysztof Parzyszek
364f2492a3 [Hexagon] Revert r274381: that was actually wrong
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274384 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-01 20:45:19 +00:00
Krzysztof Parzyszek
7993722a44 [Hexagon] Use MachineOperand::readsReg instead of isUse
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274381 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-01 20:28:30 +00:00
Duncan P. N. Exon Smith
a204da23db CodeGen: Use MachineInstr& in TargetLowering, NFC
This is a mechanical change to make TargetLowering API take MachineInstr&
(instead of MachineInstr*), since the argument is expected to be a valid
MachineInstr.  In one case, changed a parameter from MachineInstr* to
MachineBasicBlock::iterator, since it was used as an insertion point.

As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274287 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-30 22:52:52 +00:00
Rafael Espindola
9931d67967 Delete MCCodeGenInfo.
MC doesn't really care about CodeGen stuff, so this was just
complicating target initialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274258 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-30 18:25:11 +00:00
Rafael Espindola
809018e56e Delete unused includes. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274225 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-30 12:19:16 +00:00
Duncan P. N. Exon Smith
567409db69 CodeGen: Use MachineInstr& in TargetInstrInfo, NFC
This is mostly a mechanical change to make TargetInstrInfo API take
MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator)
when the argument is expected to be a valid MachineInstr.  This is a
general API improvement.

Although it would be possible to do this one function at a time, that
would demand a quadratic amount of churn since many of these functions
call each other.  Instead I've done everything as a block and just
updated what was necessary.

This is mostly mechanical fixes: adding and removing `*` and `&`
operators.  The only non-mechanical change is to split
ARMBaseInstrInfo::getOperandLatencyImpl out from
ARMBaseInstrInfo::getOperandLatency.  Previously, the latter took a
`MachineInstr*` which it updated to the instruction bundle leader; now,
the latter calls the former either with the same `MachineInstr&` or the
bundle leader.

As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.

Note: I updated WebAssembly, Lanai, and AVR (despite being
off-by-default) since it turned out to be easy.  I couldn't run tests
for AVR since llc doesn't link with it turned on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274189 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-30 00:01:54 +00:00
Rafael Espindola
c4cbe67fa8 Use isPositionIndependent in a few more places.
I think this converts all the simple cases that really just care about
the generated code being position independent or not. The remaining
uses are a bit more complicated and are checking things like "is this
a library or executable" or "can this symbol be preempted".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274055 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-28 20:13:36 +00:00
Rafael Espindola
d980ed0d00 Move shouldAssumeDSOLocal to Target.
Should fix the shared library build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273958 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27 23:15:57 +00:00
Krzysztof Parzyszek
339dc3dc8f [Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273885 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27 15:08:22 +00:00
Rafael Espindola
608ab75c0b Use isPositionIndependent predicate. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273827 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-26 22:24:01 +00:00
Krzysztof Parzyszek
99719f40ee [Hexagon] Simplify (+fix) instruction selection for indexed loads/stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273733 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-24 21:27:17 +00:00
Nirav Dave
218e5843a6 Preserve DebugInfo when replacing values in DAGCombiner
Recommiting after correcting over-eager Debug Value transfer fixing PR28270.

[DAG] Previously debug values would transfer debuginfo for the selected
start node for a replacement which allows for debug to be dropped.

Push debug value transfer to occur with node/value replacement in
SelectionDAG, remove now extraneous transfers of debug values.

This refixes PR9817 which was being incompletely checked in the
testsuite.

Reviewers: jyknight

Subscribers: dblaikie, llvm-commits

Differential Revision: http://reviews.llvm.org/D21037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273585 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-23 17:52:57 +00:00
Peter Collingbourne
7cbcee7cad Revert r273456, "Preserve DebugInfo when replacing values in DAGCombiner" as it caused pr28270.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273518 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-23 00:06:17 +00:00
Reid Kleckner
26f1ddead4 Prune some includes from headers and sink some inline functions
MCSymbol.h shouldn't pull in MCAssembler.h, just MCFragment.h.
MCLinkerOptimizationHint.h shouldn't need MCMachObjectWriter.h.  The
rest is fixing the fallout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273507 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-22 23:23:08 +00:00
Krzysztof Parzyszek
c7a10fc5ed [Hexagon] Add SDAG preprocessing step to expose shifted addressing modes
Transform: (store ch addr (add x (add (shl y c) e)))
       to: (store ch addr (add x (shl (add y d) c))),
where e = (shl d c) for some integer d.
The purpose of this is to enable generation of loads/stores with
shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift
value c must be 0, 1 or 2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273466 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-22 20:08:27 +00:00
Rafael Espindola
5e5a33df9e Start using shouldAssumeDSOLocal on Hexagon.
Include a token test showing that access to private is now the same as
to internal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273457 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-22 19:09:14 +00:00
Nirav Dave
123be93bcd Preserve DebugInfo when replacing values in DAGCombiner
Recommiting after fixing over-aggressive assertion

[DAG] Previously debug values would transfer debuginfo for the selected
start node for a replacement which allows for debug to be dropped.

Push debug value transfer to occur with node/value replacement in
SelectionDAG, remove now extraneous transfers of debug values.

This refixes PR9817 which was being incompletely checked in the
testsuite.

Reviewers: jyknight

Subscribers: dblaikie, llvm-commits

Differential Revision: http://reviews.llvm.org/D21037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273456 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-22 19:03:26 +00:00
Krzysztof Parzyszek
065537a5a0 [Hexagon] Handle expansion of cmpxchg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273432 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-22 16:07:10 +00:00
Krzysztof Parzyszek
d140aab2ca [SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCallee
The setCallee function will set the number of fixed arguments based
on the size of the argument list. The FixedArgs parameter was often
explicitly set to 0, leading to a lack of consistent value for non-
vararg functions.

Differential Revision: http://reviews.llvm.org/D20376


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273403 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-22 12:54:25 +00:00
Rafael Espindola
95ba82925b Delete more dead code.
Found by gcc 6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273322 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-21 21:51:41 +00:00
David Majnemer
c1362817c9 Replace silly uses of 'signed' with 'int'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273244 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-21 05:10:24 +00:00
Nirav Dave
e9d4816026 Refactor and cleanup Assembly Parsing / Lexing
Recommiting after fixing non-atomic insert to front of SmallVector in
MCAsmLexer.h

Add explicit Comment Token in Assembly Lexing for future support for
outputting explicit comments from inline assembly. As part of this,
CPPHash Directives are now explicitly distinguished from Hash line
comments in Lexer.

Line comments are recorded as EndOfStatement tokens, not Comment tokens
to simplify compatibility with current TargetParsers. This slightly
complicates comment output.

This remove all lexing tasks out of the parser, does minor cleanup
to remove extraneous newlines Asm Output, and some improvements white
space handling.

Reviewers: rtrieu, dwmw2, rnk

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273007 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-17 16:06:17 +00:00
Nirav Dave
afacc9421f Revert "Refactor and cleanup Assembly Parsing / Lexing"
Reverting for unexpected crashes on various platforms.

This reverts commit r272953.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272957 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-16 21:19:23 +00:00
Nirav Dave
e0348ce1ac Refactor and cleanup Assembly Parsing / Lexing
Add explicit Comment Token in Assembly Lexing for future support for
outputting explicit comments from inline assembly. As part of this,
CPPHash Directives are now explicitly distinguished from Hash line
comments in Lexer.

Line comments are recorded as EndOfStatement tokens, not Comment tokens
to simplify compatibility with current TargetParsers. This slightly
complicates comment output.

This remove all lexing tasks out of the parser, does minor cleanup
to remove extraneous newlines Asm Output, and some improvements white
space handling.

Reviewers: rtrieu, dwmw2, rnk

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272953 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-16 20:34:22 +00:00
Krzysztof Parzyszek
16185a2b7f [Hexagon] Fix/simplify some conditional statements
Fix for PR28138.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272836 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-15 21:05:04 +00:00
Nirav Dave
63a4b3937b Revert "Preserve DebugInfo when replacing values in DAGCombiner"
Reverting due to assertion failure in
lib/CodeGen/SelectionDAG/InstrEmitter.cpp

This reverts commit r272792.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272799 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-15 16:08:50 +00:00
Nirav Dave
d2f1fe5fc1 Preserve DebugInfo when replacing values in DAGCombiner
[DAG] Previously debug values would transfer debuginfo for the selected
start node for a replacement which allows for debug to be dropped.

Push debug value transfer to occur with node/value replacement in
SelectionDAG, remove now extraneous transfers of debug values.

This refixes PR9817 which was being incompletely checked in the
testsuite.

Reviewers: jyknight

Subscribers: dblaikie, llvm-commits

Differential Revision: http://reviews.llvm.org/D21037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272792 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-15 14:50:08 +00:00
Benjamin Kramer
13c42d2b20 Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.
No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272516 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-12 17:30:47 +00:00
Benjamin Kramer
af18e017d2 Pass DebugLoc and SDLoc by const ref.
This used to be free, copying and moving DebugLocs became expensive
after the metadata rewrite. Passing by reference eliminates a ton of
track/untrack operations. No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272512 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-12 15:39:02 +00:00
Krzysztof Parzyszek
96e0dbfb1a [Hexagon] Remove incorrect offset scaling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272399 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-10 15:43:18 +00:00
Krzysztof Parzyszek
7bf435bbe7 [Hexagon] Modify HexagonExpandCondsets to handle subregisters
Also, switch to using functions from LiveIntervalAnalysis to update
live intervals, instead of performing the updates manually.

Re-committing r272045.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272135 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-08 12:31:16 +00:00
Benjamin Kramer
04a303b821 Avoid copies of std::strings and APInt/APFloats where we only read from it
As suggested by clang-tidy's performance-unnecessary-copy-initialization.
This can easily hit lifetime issues, so I audited every change and ran the
tests under asan, which came back clean.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272126 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-08 10:01:20 +00:00
Krzysztof Parzyszek
6fc4b2ad52 Revert r272045 since GCC doesn't know how to compile it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272048 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-07 19:25:28 +00:00
Krzysztof Parzyszek
01da260d54 [Hexagon] Modify HexagonExpandCondsets to handle subregisters
Also, switch to using functions from LiveIntervalAnalysis to update
live intervals, instead of performing the updates manually.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272045 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-07 19:06:23 +00:00
Chandler Carruth
ddda8d8de8 Remove bogus initialization of the PPC and Hexagon SelectionDAGISel
subclasses. These are not passes proper. We don't support registering
them, they can't be constructed with default arguments, and the ID is
actually in a base class.

Only these two targets even had any boiler plate to try to do this, and
it had to be munged out of the INITIALIZE_PASS macros to work. What's
worse, the boiler plate has rotted and the "name" of the pass is
actually the description string now!!! =/ All of this is completely
unnecessary. No other target bothers, and nothing breaks if you don't
initialize them because CodeGen has an entirely separate initialization
path that is somewhat more durable than relying on the implicit
initialization the way the 'opt' tool does for registered passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271650 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-03 10:13:31 +00:00