104572 Commits

Author SHA1 Message Date
Zachary Turner
c1422a59e8 [lld/pdb] Create an empty public symbol record stream.
This is part of the continuing effort to increase parity between
LLD and MSVC PDBs.  link still doesn't like our PDBs, so the most
obvious thing to check was whether adding an empty publics stream
would get it to do something else.  It still fails in the same way
but at least this removes one more variable from the equation.
The next logical step would be to try creating an empty globals
stream.

Differential Revision: https://reviews.llvm.org/D35224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307598 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 22:40:20 +00:00
Joel Jones
6ed70a89d6 Doxygen formatting. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307597 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 22:11:50 +00:00
Matthias Braun
c364d94de8 Revert "[DAG] Improve Aliasing of operations to static alloca"
Reverting as it breaks tramp3d-v4 in the llvm test-suite. I added some
comments to https://reviews.llvm.org/D33345 about it.

This reverts commit r307546.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307589 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 20:51:30 +00:00
Leo Li
581e763cd4 [ConstantHoisting] Remove dupliate logic in constant hoisting
Summary:
As metioned in https://reviews.llvm.org/D34576, checkings in
`collectConstantCandidates` can be replaced by using
`llvm::canReplaceOperandWithVariable`.

The only special case is that `collectConstantCandidates` return false for
all `IntrinsicInst` but it is safe for us to collect constant candidates from
`IntrinsicInst`.

Reviewers: pirama, efriedma, srhines

Reviewed By: efriedma

Subscribers: llvm-commits, javed.absar

Differential Revision: https://reviews.llvm.org/D34921

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307587 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 20:45:34 +00:00
Davide Italiano
063d8f6b0f [NewGVN] Simplify a lambda a little bit. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307586 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 20:45:00 +00:00
Nirav Dave
c7acbe2ea6 Add DAG argument to canMergeStoresTo NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307583 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 20:25:54 +00:00
Krzysztof Parzyszek
7a9373cdbb [Hexagon] Convert typed ISD opcodes to generic ones, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307582 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 20:16:44 +00:00
Farhana Aleen
b0d5344402 Avoid doing conservative phi checks in aliasSameBasePointerGEPs() if no phis have been visited yet.
Reviewers: Daniel Berlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34478

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307581 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 20:15:40 +00:00
Krzysztof Parzyszek
d07ce5fb3f [Hexagon] Remove unused ISD opcodes, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307580 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 20:13:44 +00:00
Dehao Chen
a569cab404 Use DenseMap instead std::map for GVSummaryMapTy.
Summary: This speeds-up thin-link by ~47% for large programs.

Reviewers: tejohnson

Reviewed By: tejohnson

Subscribers: sanjoy, llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D35148

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307578 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 20:12:54 +00:00
Matt Arsenault
d380c14b7a AMDGPU: Allow SIShrinkInstructions to fold FrameIndexes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307576 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 20:04:35 +00:00
Matt Arsenault
a038a8340c AMDGPU: Allow SIShrinkInstructions to work in non-SSA
Immediates can be folded as long as the immediate is a vreg.

Also undo commuting instructions if it didn't fold an immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307575 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 19:53:57 +00:00
Matt Arsenault
7231966089 AMDGPU: Remove unnecessary check for constant operands
An instruction that has an immediate operand can't reach
this point. This is only called for a freshly shrunk instruction,
which prevously couldn't have had a literal constant operand.
This was also not conservative enough since it woudl also have
had to filter other constant-like inputs like frame indexes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307574 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 19:33:38 +00:00
Konstantin Zhuravlyov
f392c1f922 AMDGPU: Do not test for SI in getIsaVersion
SI is being tested by isa version in the first two if statements of the function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307573 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 19:24:05 +00:00
Krzysztof Parzyszek
33287d8a69 [Hexagon] Fix check for HMOTF_ConstExtend operand flag
This fixes https://llvm.org/PR33718.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307566 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 18:38:52 +00:00
Sam Clegg
589c8caef1 [WebAssembly] Use the correct size for MCFillFragment
Summary: When implementing MCFillFragment, use the size of the fragment,
rather than the size of the section.

Patch by Dan Gohman

Differential Revision: https://reviews.llvm.org/D35090

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307565 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 18:36:34 +00:00
Krzysztof Parzyszek
374ba004d2 [Hexagon] Handle Hexagon-specific machine operand target flags in MIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307564 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 18:31:02 +00:00
Tony Jiang
dc4a67cca0 [PPC CodeGen] Expand the bitreverse.i64 intrinsic.
Differential Revision: https://reviews.llvm.org/D34908
Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307563 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 18:11:23 +00:00
Serge Guelton
65eefa7f01 Fix invalid cast in instcombine UMul/ZExt idiom
Fixes https://bugs.llvm.org/show_bug.cgi?id=25454

Do not assume IRBuilder creates Instruction where it can create Value.
Do not assume idiom operands are constant, leave generalisation ot the IRBuilder.

Differential Revision: https://reviews.llvm.org/D35114


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307554 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 16:51:40 +00:00
Lei Huang
b6988767a8 [PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.
For this example:
float test (int *arr) {
    return arr[2];
}

We currently generate the following code:
  li r4, 8
  lxsiwax f0, r3, r4
  xscvsxdsp f1, f0

With this patch, we will now generate:
  addi r3, r3, 8
  lxsiwax f0, 0, r3
  xscvsxdsp f1, f0

Originally reported in: https://bugs.llvm.org/show_bug.cgi?id=27204
Differential Revision: https://reviews.llvm.org/D35027

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307553 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 16:44:45 +00:00
Andrew V. Tischenko
0fd6ce773d [X86] Model 256-bit AVX instructions in the AMD Jaguar scheduler Part-1 (PR28573).
The new version of the model is definitely faster.

Differential Revision:
https://reviews.llvm.org/D35198


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307552 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 16:36:03 +00:00
Nirav Dave
e791f411d3 [DAG] Improve Aliasing of operations to static alloca
Memory accesses offset from frame indices may alias, e.g., we
may merge write from function arguments passed on the stack when they
are contiguous. As a result, when checking aliasing, we consider the
underlying frame index's offset from the stack pointer.

Static allocs are realized as stack objects in SelectionDAG, but its
offset is not set until post-DAG causing DAGCombiner's alias check to
consider access to static allocas to frequently alias. Modify isAlias
to consider access between static allocas and access from other frame
objects to be considered aliasing.

Many test changes are included here. Most are fixes for tests which
indirectly relied on our aliasing ability and needed to be modified to
preserve their original intent.

The remaining tests have minor improvements due to relaxed
ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll
which has a minor degradation dispite though the pre-legalized DAG is
improved.

Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand

Reviewed By: rnk

Subscribers: sdardis, nemanjai, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307546 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 15:39:41 +00:00
Anna Thomas
5be3d3e74b [LoopUnrollRuntime] Remove strict assert about VMap requirement
When unrolling under multiple exits which is under off-by-default option,
the assert that checks for VMap entry in loop exit values is too strong.
(assert if VMap entry did not exist, the value should be a
constant). However, values derived from
constants or from values outside loop, does not have a VMap entry too.

Removed the assert and added a testcase showcasing the property for
non-constant values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307542 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 15:29:38 +00:00
Hiroshi Inoue
58d2b3aa33 fix typos in comments and error messages; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307533 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 12:44:25 +00:00
Philip Pfaffe
19045617b3 [PM] Enable registration of out-of-tree passes with PassBuilder
Summary:
This patch adds a callback registration API to the PassBuilder,
enabling registering out-of-tree passes with it.

Through the Callback API, callers may register callbacks with the
various stages at which passes are added into pass managers, including
parsing of a pass pipeline as well as at extension points within the
default -O pipelines.

Registering utilities like `require<>` and `invalidate<>` needs to be
handled manually by the caller, but a helper is provided.

Additionally, adding passes at pipeline extension points is exposed
through the opt tool. This patch adds a `-passes-ep-X` commandline
option for every extension point X, which opt parses into pipelines
inserted into that extension point.

Reviewers: chandlerc

Reviewed By: chandlerc

Subscribers: lksbhm, grosser, davide, mehdi_amini, llvm-commits, mgorny

Differential Revision: https://reviews.llvm.org/D33464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307532 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 10:57:55 +00:00
Javed Absar
e9e97c867a [ARM] Tidy up ARMBaseRegisterInfo implementation. NFC
Clean up ARMBaseRegisterInfo implementation a bit.
Differential Revision: https://reviews.llvm.org/D35116



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307531 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 10:42:55 +00:00
George Rimar
72f54aa84f [DWARF] - Rename variable. NFC.
Variable was called 'Name' and contained text
name of relocation type. Problem was that
outside of this error handling scope we already
have different 'Name' variable that contains
section name.

Change helps to avoid confusion. 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307530 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 10:04:51 +00:00
Gadi Haber
33dd96a273 This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.

Please note that the patch extensively affects the X86 MC instr scheduling for SNB.

Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.

The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs

For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:

def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];

}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;

Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.

Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb

Differential Revision:  https://reviews.llvm.org/D35019#inline-304691




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307529 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 09:53:16 +00:00
George Rimar
505b8a7283 [DWARF] - Remove unused variables. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307528 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 09:36:44 +00:00
Igor Breger
8c3ce14ba8 [GlobalISel][X86] Support G_LOAD/G_STORE i1.
Summary: Support G_LOAD/G_STORE i1.

Reviewers: zvi, guyblank

Reviewed By: guyblank

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D35178

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307527 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 09:26:09 +00:00
Igor Breger
77954ced1a [GlobalISel][X86] extend G_ZEXT support.
Summary:
Mark G_ZEXT/G_SEXT i1 to i8/i16,  i8 to i16 as legal.
Support G_ZEXT i1 to i8/i16 instruction selection ( C++ code).
This patch requred to support G_LOAD/G_STORE i1.

Reviewers: zvi, guyblank

Reviewed By: guyblank

Subscribers: rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D35177

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307526 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 09:07:34 +00:00
Hiroshi Inoue
9086ed9db0 fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307523 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 06:32:52 +00:00
Craig Topper
12a230f4b4 [X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307522 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 06:09:22 +00:00
Mikael Holmen
3c7da1cd61 [ArgumentPromotion] Change use of removed argument in llvm.dbg.value to undef
Summary:
This solves PR33641.

When removing a dead argument we must also handle possibly existing calls
to llvm.dbg.value that use the removed argument. Now we change the use
of the otherwise dead argument to an undef for some other pass to cleanup
later.

If the calls are left untouched, they will later on cause errors:
 "function-local metadata used in wrong function"
since the ArgumentPromotion rewrites the code by creating a new function
with the wanted signature, but the metadata is not recreated so the new
function may then erroneously use metadata from the old function.

Reviewers: mstorsjo, rnk, arsenm

Reviewed By: rnk

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D34874

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307521 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 06:07:24 +00:00
Craig Topper
d76565ff5f [X86] Remove asserts from getX86CpuIDAndInfo/getX86CpuIDAndInfoEx. Restore past behavior of returning an unsupported indication to the caller instead.
These asserts could only occur if we fail to properly detect the compiler, but an assert is not a good way to do that because it doesn't work in release builds.

I wonder if we could use #error?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307520 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 06:04:11 +00:00
David Blaikie
cb16061ea7 llvm-profdata: Reduce memory usage by using Error callback rather than member
Reduces llvm-profdata memory usage on a large profile from 7.8GB to 5.1GB.

The ProfData API now supports reporting all the errors/warnings rather
than only the first, though llvm-profdata ignores everything after the
first for now to preserve existing behavior. (if there's a desire for
other behavior, happy to implement that - but might be as well left for
a separate patch)

Reviewers: davidxl

Differential Revision: https://reviews.llvm.org/D35149

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307516 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-10 03:04:59 +00:00
Davide Italiano
e7b6244965 [X86] Relax an assertion when legalizing vector types.
WidenVSELECTAndMask can fold (and it folds in this case) so we
get a BUILD_VECTOR of constants as mask. convertMask() seems to
work fine when the input is a vector of constants, and we still
need to call it to extend/add elements at the end. but the current
code just asserts on anything but a SETCC or AND/OR/XOR of 2xSETCC.
This change was discussed briefly with Simon Pilgrim, who also
suggests we might consider dropping this assertion in the future.

Fixes PR33715.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307508 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 19:22:48 +00:00
Simon Pilgrim
6c560b5efb [X86] Allow GHC calling convention to use YMM and ZMM registers
GHC 8.4 will know how to use YMM and ZMM registers for calls.

Submitted on behalf of @bgamari (Ben Gamari)

Differential Revision: https://reviews.llvm.org/D34854 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307504 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 16:57:10 +00:00
Simon Pilgrim
3b637f6281 Handle ConstantExpr correctly in SelectionDAGBuilder
This change fixes a bug in SelectionDAGBuilder::visitInsertValue and SelectionDAGBuilder::visitExtractValue where constant expressions (InsertValueConstantExpr and ExtractValueConstantExpr) would be treated as non-constant instructions (InsertValueInst and ExtractValueInst). This bug resulted in an incorrect memory access, which manifested as an assertion failure in SDValue::SDValue.

Fixes PR#33094.

Submitted on behalf of @Praetonus (Benoit Vey)

Differential Revision: https://reviews.llvm.org/D34538

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307502 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 16:01:04 +00:00
Chandler Carruth
fe40a5a3de [PM] Fix a nasty bug in the new PM where we failed to properly
invalidation of analyses when merging SCCs.

While I've added a bunch of testing of this, it takes something much
more like the inliner to really trigger this as you need to have
partially-analyzed SCCs with updates at just the right time. So I've
added a direct test for this using the inliner and verifying the
domtree. Without the changes here, this test ends up finding a stale
dominator tree.

However, to handle this properly, we need to invalidate analyses
*before* merging the SCCs. After talking to Philip and Sanjoy about this
they convinced me this was the right approach. To do this, we need
a callback mechanism when merging SCCs so we can observe the cycle that
will be merged before the merge happens. This API update ended up being
surprisingly easy.

With this commit, the new PM passes the test-suite again. It hadn't
since MemorySSA was enabled for EarlyCSE as that also will find this bug
very quickly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307498 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 13:45:11 +00:00
Chandler Carruth
b86a95f1b6 [PM] Add unittesting of the call graph update logic with complex
dependencies between analyses.

This uncovers even more issues with the proxies and the splitting apart
of SCCs which are fixed in this patch. I discovered this while trying to
add more rigorous testing for a change I'm making to the call graph
update invalidation logic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307497 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 13:16:55 +00:00
Craig Topper
a0e7d65aa6 [X86] Remove check for AVX512 support from skylake-avx512 detection in getHostCPUName.
Users of getHostCPUName should also use getHostCPUFeatures which will take care of making sure avx512 is disabled if the CPU doesn't support it. This is consistent with what we do for other CPUs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307495 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 07:26:14 +00:00
Craig Topper
eb41f6a345 [IR] Add Type::isIntOrIntVectorTy(unsigned) similar to the existing isIntegerTy(unsigned), but also works for vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307492 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 07:04:03 +00:00
Craig Topper
1060082924 [IR] Make use of Type::isPtrOrPtrVectorTy/isIntOrIntVectorTy/isFPOrFPVectorTy to shorten code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307491 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 07:04:00 +00:00
Igor Breger
7e96a89b3c [FastISel] fix a fallback diagnostic.
Summary: FastISel was marked as failed in case instruction selection succeeded.

Reviewers: qcolombet, zvi, rovka, ab

Reviewed By: zvi

Subscribers: javed.absar, ab, qcolombet, bogner, llvm-commits

Differential Revision: https://reviews.llvm.org/D34438

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307489 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 05:55:20 +00:00
Hiroshi Inoue
5c99c6a26a fix trivial typos; NFC
sucessor -> successor 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307488 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 05:54:44 +00:00
Chandler Carruth
143ef32e8f [PM] Finish implementing and fix a chain of bugs uncovered by testing
the invalidation propagation logic from an SCC to a Function.

I wrote the infrastructure to test this but didn't actually use it in
the unit test where it was designed to be used. =[ My bad. Once
I actually added it to the test case I discovered that it also hadn't
been properly implemented, so I've implemented it. The logic in the FAM
proxy for an SCC pass to propagate invalidation follows the same ideas
as the FAM proxy for a Module pass, but the implementation is a bit
different to reflect the fact that it is forwarding just for an SCC.

However, implementing this correctly uncovered a surprising "bug" (it
was conservatively correct but relatively very expensive) in how we
handle invalidation when splitting one SCC into multiple SCCs. We did an
eager invalidation when in reality we should be deferring invaliadtion
for the *current* SCC to the CGSCC pass manager and just invaliating the
newly constructed SCCs. Otherwise we end up invalidating too much too
soon. This was exposed by the inliner test case that I've updated. Now,
we invalidate *just* the split off '(test1_f)' SCC when doing the CG
update, and then the inliner finishes and invalidates the '(test1_g,
test1_h)' SCC's analyses. The first few attempts at fixing this hit
still more bugs, but all of those are covered by existing tests. For
example, the inliner should also preserve the FAM proxy to avoid
unnecesasry invalidation, and this is safe because the CG update
routines it uses handle any necessary adjustments to the FAM proxy.

Finally, the unittests for the CGSCC pass manager needed a bunch of
updates where we weren't correctly preserving the FAM proxy because it
hadn't been fully implemented and failing to preserve it didn't matter.

Note that this doesn't yet fix the current crasher due to MemSSA finding
a stale dominator tree, but without this the fix to that crasher doesn't
really make any sense when testing because it relies on the proxy
behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307487 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 03:59:31 +00:00
Craig Topper
1e0e5aa155 [InstCombine] Speculatively implement a fix for what might be the root cause of PR33721 by making sure that we have integer types before doing select C, -1, 0 -> sext C to int
I recently changed m_One and m_AllOnes to use Constant::isOneValue/isAllOnesValue which work on floating point values too. The original implementation looked specifically for ConstantInt scalars and splats. So I'm guessing we are accidentally trying to issue sext/zexts on floating point types now.

Hopefully I figure out how to reproduce the failure from the PR soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307486 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-09 03:25:17 +00:00
Simon Pilgrim
db24b6e4f7 [AMDGPU] Fix -Wimplicit-fallthrough warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307485 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-08 19:50:03 +00:00
Simon Pilgrim
a24a9b84eb [AArch64] Fix -Wimplicit-fallthrough warnings. NFCI.
Add breaks - doesn't affect results as both GPR/FPU both check for 32/64 bit sizes. So will still default to GenericOps in the same way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307484 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-08 19:28:24 +00:00