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3927 Commits

Author SHA1 Message Date
NAKAMURA Takumi
b0c95fbaf9 lit/TestRunner.py: Use RemoveForce(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145223 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 01:55:08 +00:00
NAKAMURA Takumi
fc1a1870b5 lit/TestRunner.py: [Win32] Introduce WinWaitReleased(f), to wait for file handles to be released by children. 
When wait() has finished, opened handles (especially writing stdout to file) might not be released immediately.
To wait for released, poll to attempt renaming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145222 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-28 01:55:01 +00:00
Craig Topper
787a88ff18 Remove some unnecessary filtering checks from X86 disassembler table build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-19 05:48:20 +00:00
Daniel Dunbar
d5889d8c7f llvm-build: Attempt to work around a CMake Makefile generator bug that doesn't 
properly quote strings when writing the CMakeFiles/Makefile.cmake output file
(which lists the dependencies). This shows up when using CMake + MSYS Makefile
generator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-17 01:19:53 +00:00
Owen Anderson
99aa14ff64 Rename MVT::untyped to MVT::Untyped to match similar nomenclature. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-16 01:02:57 +00:00
Evan Cheng
eaa192af18 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 02:12:34 +00:00
Jim Grosbach
bfc9429c2b ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 01:46:57 +00:00
Jim Grosbach
2a8cd57566 Tidy up. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144598 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 01:05:12 +00:00
Daniel Dunbar
e9d05d27e8 LLVMBuild: Add info for gtest. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144445 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-12 02:11:04 +00:00
Daniel Dunbar
8396893fa5 LLVMBuild: Alphabetize required_libraries lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144416 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 22:59:23 +00:00
Daniel Dunbar
b7f3bfc559 llvm-build: Add --configure-target-def-file option. 
- Can be used to generate the substitution values we currently use for the various target related .def files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 00:24:00 +00:00
Daniel Dunbar
5ed5506f18 LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 00:23:56 +00:00
Daniel Dunbar
8333730259 build/Make & CMake: Pass the appropriate --native-target and --enable-targets 
options to llvm-build, so the all-targets etc. components are defined properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 01:16:48 +00:00
Daniel Dunbar
affc6cf9d2 llvm-build: Add --native-target and --enable-targets options, and add logic to 
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144253 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:50:07 +00:00
Daniel Dunbar
b4eaee7a44 llvm-build: Split out the validation logic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:49:58 +00:00
Daniel Dunbar
c352caf168 llvm-build: Add an explicit component type to represent targets. 
- Gives us a place to hang target specific metadata (like whether the target has a JIT).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:49:51 +00:00
Daniel Dunbar
1e5b24330b llvm-build: Tidy up options. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144249 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:49:42 +00:00
Owen Anderson
1ad1246bbc Remove this from the CMake build since I erased the file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 00:07:22 +00:00
Owen Anderson
a25e292d5f Remove the old-style ARM disassembler, which is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144243 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:56:06 +00:00
Craig Topper
c8eb880a7f More AVX2 instructions and their intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-06 23:04:08 +00:00
Daniel Dunbar
195c6f3663 utils/llvm-build: Ensure output directory exists for tools which write various fragments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143782 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-05 04:07:49 +00:00
Daniel Dunbar
57574fa35e utils/llvm-build: Add trivial quoting of slashes for CMake fragment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-05 04:07:43 +00:00
Daniel Dunbar
20fb32b392 llvm-build: Quote colons in target names, in an attempt to make msys happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143745 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 23:40:11 +00:00
Daniel Dunbar
1688961d4e llvm-build: Add initial --write-cmake-fragment option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143744 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 23:10:37 +00:00
Bob Wilson
fb067ed485 Build llvmCore with RTTI enabled. <rdar://problem/10395761> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 17:57:13 +00:00
Daniel Dunbar
903aa8d00f utils: Rename the "llvmbuild" script to llvm-compilers-check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143673 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-04 01:09:02 +00:00
Daniel Dunbar
02271a7b42 llvm-build: Add initial code for --write-make-fragment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143661 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 22:46:19 +00:00
Daniel Dunbar
89b6f2ea9f utils: Remove (way) old nightly test scripts, I don't think anyone uses them and LNT has way better tools than this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143655 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 21:03:53 +00:00
Daniel Dunbar
e10233b668 llvm-build: Avoid followlinks keyword argument to os.walk. 
- llvm-build should now be Python2.4 compatible as best I know.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 19:45:52 +00:00
Daniel Dunbar
a3a2dfd4a2 build: Add initial cut at LLVMBuild.txt files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 18:53:17 +00:00
Daniel Dunbar
fb6d79a58e llvm-build: Update --write-llvmbuild to write out a standard LLVM style file 
header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 17:56:31 +00:00
Daniel Dunbar
efe2f644ec llvm-build: Add "--write-library-table" option for generating the C++ library 
dependency table used by llvm-config.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143628 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 17:56:28 +00:00
Daniel Dunbar
43120df44b llvm-build: Add --write-llvmbuild option, which writes out the component tree. 
- Useful for migrating or auto-upgrading the format schema.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 17:56:21 +00:00
Daniel Dunbar
00b4b4f5cb llvm-build: Add --print-tree command line option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 17:56:18 +00:00
Daniel Dunbar
86c119a507 llvm-build: Fill in some details w.r.t. component's parents. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143624 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 17:56:16 +00:00
Daniel Dunbar
1cf14aff1b llvm-build: Validate information on the loaded components and form the topological ordering among them (as well as validating that there are no cycles). 
- Currently we require that all references between components (except the parent relation) fit into a DAG -- this could be relaxed later if it ever proves to be useful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143623 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 17:56:12 +00:00
Daniel Dunbar
9da6b12441 llvm-build: Fill in more of component parsing to be more strict and 
differentiate between strings and lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 17:56:10 +00:00
Daniel Dunbar
df578254a1 llvm-build: Sketch code to load LLVMBuild.txt files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143621 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 17:56:06 +00:00
Daniel Dunbar
ad5e0122c1 build: Stub out llvm-build utility tool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143620 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-03 17:56:03 +00:00
Chandler Carruth
1bfc9f8ff2 The TableGen parts of the CMake build are seriously broken. This fixes 
one aspect of them by having them use the (annoying, if not broken)
proper library dependency model for adding the LLVMTableGen library as
a dependency. This could manifest as a link order issue in the presence
of separate LLVM / Clang source builds with CMake and a linker that
really cares about such things.

Also, add the Support dependency to llvm-tblgen itself so that it
doesn't rely on TableGen's transitive Support dependency. A parallel
change for clang-tblgen will be forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 05:03:06 +00:00
Chad Rosier
3eae0c2fa6 Rename show-diagnostics to something less ambiguous. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143525 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-02 00:44:16 +00:00
Bill Wendling
ac6d7e4911 Do a relative path ln command instead of an absolute path one. Some people strangely enough have different directory layouts... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143302 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-29 23:49:52 +00:00
Jim Grosbach
48c1f84b10 Allow InstAlias's to use immediate matcher patterns that xform the value. 
For example,

On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:32:53 +00:00
Jim Grosbach
be5d6bcfc6 Allow register classes to match a containing class in InstAliases. 
If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 16:43:40 +00:00
Dan Gohman
33ba8b0e96 Remove the Alpha backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143164 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 22:56:32 +00:00
Jim Grosbach
e39102819e Delete dead code. Nothing ever instantiates this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 21:59:17 +00:00
Daniel Dunbar
241f997d3a lit: Drop some unneeded code from example tests. 
- Also, cleanup site.exp files in example tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143141 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 20:59:19 +00:00
Dan Gohman
3e6157de57 Remove the Blackfin backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142880 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-25 00:05:42 +00:00
Dan Gohman
29074ccf6c Remove the SystemZ backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 23:48:32 +00:00
Chad Rosier
7f53d592ff Add options to enable each individual level for the show-diagnostics tool. 
rdar://9683410

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142856 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 21:56:50 +00:00
Bill Wendling
65ec521c3c Rename the script to indicate that this is for the TEST=simple tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142764 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-23 20:14:06 +00:00
Bill Wendling
aec4011947 Resurrect the 'find regressions for the TEST=nightly tests' script. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-23 20:13:14 +00:00
Craig Topper
75485d6746 Add X86 RORX instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-23 07:34:00 +00:00
Benjamin Kramer
1a2f9886a2 Move various generated tables into read-only memory, fixing up const correctness along the way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-22 16:50:00 +00:00
Jim Grosbach
4661d4cac3 Assembly parsing for 2-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db Assembly parsing for 4-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056 Assembly parsing for 3-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:54:25 +00:00
Duncan Sands
58fba239e4 Ensure timestamps are not embedded into files when doing a release build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 09:47:14 +00:00
Bill Wendling
b9ad624fcd Modify the script to output the regressions and passes into categories. My Python-fu could use some improving... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 06:58:01 +00:00
Bill Wendling
3df9f541a0 Check for divide by zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 06:26:01 +00:00
Duncan Sands
19595dc4d0 Also compare the built dragonegg objects between phases 2 and 3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 20:14:18 +00:00
Duncan Sands
fbc0dec7b4 Reset the system compiler each time we start a new flavour. Otherwise 
the last compiler built for the previous flavour is used for the next,
for example the Debug clang compiler was being used for the initial build
of the Release LLVM.  Flavors should be independent of each other.  This
especially matters if the compiler built for the previous flavour doesn't
actually work!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 20:10:58 +00:00
Duncan Sands
c1aef0884c Add support for testing dragonegg. This is disabled by default. 
In fact this commit is not intended to change anything unless you
use one of the new command line flags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142577 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 11:13:04 +00:00
Bill Wendling
3a8eaa736f Revamp the script to handle the 'TEST=simple' output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 00:45:46 +00:00
Bill Wendling
250c6801e4 Duncan pointed out that sometimes CC and CXX are used to specify the compiler. Also that the configure script takes care of finding an appropriate compiler if one's not specified. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142489 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 09:47:00 +00:00
Bill Wendling
495069e4df Use bash instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142486 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 09:25:49 +00:00
Bill Wendling
783993e795 Make changes so that this runs on FreeBSD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142482 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 08:42:07 +00:00
Joe Abbey
fffc0fe42c Adding dependencies to allow -DBUILD_SHARED_LIBS=true to complete. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-19 00:13:13 +00:00
Jim Grosbach
862019c37f ARM VTBL (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 23:02:30 +00:00
Bill Wendling
630243a8c2 Don't exit just because some early commands fail. Use the -k flag when running the checks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:27:12 +00:00
Jim Grosbach
f2f5bc60f6 ARM assembly parsing and encoding for VMOV.i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 16:18:11 +00:00
Jim Grosbach
6248a546f2 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 00:22:00 +00:00
Jim Grosbach
ea46110f57 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 23:09:09 +00:00
Jim Grosbach
0e387b2877 ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 22:26:03 +00:00
Bill Wendling
540d5b7406 Forgot to add the project name to the 'svn ls' command. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142282 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 21:45:07 +00:00
Bill Wendling
10f3210477 Add message to svn mkdir command. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142280 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 21:42:29 +00:00
Owen Anderson
684dfcf724 Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 16:56:47 +00:00
Benjamin Kramer
af482cf301 Pick low-hanging MatchEntry shrinkage fruit. 
Shaves 200k off Release-Asserts clang binaries on i386.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 16:18:09 +00:00
Bill Wendling
41adc5fb8b Don't download and compile compiler-rt, libcxx, and libcxxabi by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142185 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 08:41:20 +00:00
Bill Wendling
a854f5d6f9 Update to disable asserts. Build a phase 3 compiler, and compare phase 2 files against phase 3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142173 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 04:46:54 +00:00
Bill Wendling
1416dc29d8 Overhaul the 'test-release' script. 
This removes support for building llvm-gcc. It will eventually add support for
building other projects.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142165 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 22:44:08 +00:00
Bill Wendling
eeb58a7e6b Update the tree before applying patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142155 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 20:59:25 +00:00
Craig Topper
ee62e4f6d1 Add X86 PEXTR and PDEP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 16:50:08 +00:00
Craig Topper
b53fa8bf19 Add X86 BZHI instruction as well as BMI2 feature detection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 07:55:05 +00:00
Craig Topper
dc479c4a89 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 07:05:40 +00:00
Chris Lattner
3f2d5f60b3 Make SMDiagnostic a little more sane. Instead of passing around note/warning/error as a 
string, pass it around as an enum.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 05:43:57 +00:00
Chris Lattner
d8b7aa2613 Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance 
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 04:47:35 +00:00
Craig Topper
17730847d5 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 03:51:13 +00:00
Bill Wendling
9a6d61554f Add a helper script to create branches and tag release candidates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 02:03:18 +00:00
Bill Wendling
f4a4e3ae74 Add a script that helps merge changes into a release branch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142097 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-16 01:54:03 +00:00
Craig Topper
566f233ba6 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-15 20:46:47 +00:00
David Greene
bc5c49b6c7 Fix threads/jobs Calculation 
Pass the correct jobs and threads information to the builder.
We were underutilizing the number of jobs and threads specified
by the user.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 19:12:37 +00:00
David Greene
8e20b9456e Add Helpful Messages 
Bit just a bit more verbose about what's going on.  Print options
to make to aid debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141976 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 19:12:35 +00:00
David Greene
cdc3fbc61b Add Option to Skip Install 
Add a --no-install option to skip installing components.  This
speeds up the develop/test cycle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 19:12:34 +00:00
David Greene
d17f81343c Add Option to Skip gcc Build 
And a --no-gcc option to skip dragonegg and gcc builds.
This greatly speeds up the develop/test cycle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 19:12:33 +00:00
Craig Topper
54a11176f6 Add X86 ANDN instruction. Including instruction selection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 07:06:56 +00:00
Jakob Stoklund Olesen
ccbe603869 Ban rematerializable instructions with side effects. 
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-14 01:00:49 +00:00
Jim Grosbach
9b8f2a0b36 ARM parsing and encoding for the <option> form of LDC/STC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-12 17:34:41 +00:00
Eli Friedman
830378f662 Remove extra semicolon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 19:53:40 +00:00
Craig Topper
29480fd798 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-11 04:34:23 +00:00
Jakob Stoklund Olesen
819a2abc72 Emit full ED initializers even for pseudo-instructions. 
This should unbreak the picky buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 20:15:49 +00:00
Jakob Stoklund Olesen
a0ed0c0fcd Insert dummy ED table entries for pseudo-instructions. 
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:30:16 +00:00
Jim Grosbach
460a90540b ARM NEON assembly parsing and encoding for VDUP(scalar). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 23:56:00 +00:00
David Greene
a1b1b79be1 Remove Multidefs 
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 18:25:05 +00:00
Craig Topper
25f6dfd108 Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 05:35:38 +00:00
Peter Collingbourne
6d1409dcc5 Remove the Clang tblgen backends from LLVM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 13:21:42 +00:00
Craig Topper
7ea16b01fa Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 06:44:41 +00:00
Peter Collingbourne
de8f33c199 Build system infrastructure for multiple tblgens. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 01:51:51 +00:00
Jakob Stoklund Olesen
d9c1fa5205 Remove the TRI::getSubRegisterRegClass() hook. 
This restores my karma after I added TRI::getSubClassWithSubReg().

Register constraints are applied 'backwards'.  Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.

We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in?  The
getSubRegisterRegClass() hook did that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-06 00:08:27 +00:00
David Greene
6494af4d77 Vim Support for Multidefs 
Add vim highlighting support for multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 22:42:52 +00:00
David Greene
45e7266223 Emacs Support for Multidefs 
Add Emacs font-lock keyword support for multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 22:42:51 +00:00
Jakob Stoklund Olesen
845d2c0c77 Add TRI::getSubClassWithSubReg(RC, Idx) function. 
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.

For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.

The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.

The version provided by TableGen is usually adequate, but targets can
override.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 00:35:49 +00:00
Jakob Stoklund Olesen
dae7909be3 Properly use const_iterator. 
This should unbreak the Windows build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 20:18:39 +00:00
Jakob Stoklund Olesen
babf0569e2 Teach TableGen to infer missing register classes. 
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.

This patch implements the easiest form of register class inference:  For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.

This does create some new register classes for the targets in the tree:

ARM gets a new QQQQPR_with_ssub_0.  This class was omitted from the .td
file on purpose because it only has two registers.  InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.

PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8.  I think that might be an omission?

X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:

  GR64_with_sub_8bit
  GR64_TC_with_sub_8bit
  GR64_NOREX_with_sub_8bit
  GR64_TC_with_sub_8bit_hi

The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 15:28:49 +00:00
Jakob Stoklund Olesen
cc0c975b7d TableGen: Store all allocation orders together. 
There is no need to keep the primary order separate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 15:28:44 +00:00
Jakob Stoklund Olesen
6fea31e730 TableGen: Privatize CodeGenRegisterClass::TheDef and Name. 
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference.  All register classes must have a
name, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 15:28:08 +00:00
Jakob Stoklund Olesen
877b6d43d4 TableGen: Don't add synthetic Records to the RecordKeeper. 
The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141080 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 15:27:53 +00:00
Craig Topper
6744a17dcf Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 06:30:42 +00:00
Rafael Espindola
b3c4e26dc5 Remove last references to hotpatch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 03:08:43 +00:00
Bob Wilson
ae59e8cd4d Find the strip tool that works with the specified SDKROOT. rdar://10165908 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 18:48:16 +00:00
Craig Topper
42fbe9aa06 Fix typo in r140954. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140962 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 04:54:26 +00:00
Craig Topper
846a2dcada Fix disassembling of INVEPT and INVVPID to take operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 21:20:14 +00:00
Craig Topper
e1b4a1a07e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 19:54:56 +00:00
Peter Collingbourne
7c78888887 Move TableGen's parser and entry point into a library 
This is the first step towards splitting LLVM and Clang's tblgen executables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 16:41:13 +00:00
Bob Wilson
1cea66c3ba Subtarget getFeatureBits() returns a uint64_t, not unsigned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140928 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-01 02:47:54 +00:00
Jakob Stoklund Olesen
52e7dfadc6 Use precomputed BitVector for CodeGenRegisterClass::hasSubClass(). 
All the sub-class bit vectors are computed when first creating the
register bank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140905 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 23:47:05 +00:00
Jakob Stoklund Olesen
c8e2bb68bb Store sub-class lists as a bit vector. 
This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 22:19:07 +00:00
Jakob Stoklund Olesen
b7359e384f Extract a slightly more general BitVector printer. 
This one can also print 32-bit groups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140897 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 22:18:54 +00:00
Jakob Stoklund Olesen
f9a4bb78da Compute lists of super-classes in CodeGenRegisterClass. 
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 22:18:45 +00:00
David Greene
1045a594e6 Implement VarListElementInit:: resolveListElementReference 
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 20:59:49 +00:00
Jakob Stoklund Olesen
203e0b17dd Precompute a bit vector of register sub-classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140827 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 00:10:40 +00:00
Jakob Stoklund Olesen
7dcaa5b0fb Order register classes topologically. 
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140826 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 00:10:36 +00:00
Jakob Stoklund Olesen
29f018cee6 Switch to ArrayRef<CodeGenRegisterClass*>. 
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 22:28:37 +00:00
Daniel Dunbar
caf1912893 tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and 
"show-in-system-header" bits, which I will be adding in Clang shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 00:29:04 +00:00
Bob Wilson
05a5c109e0 Remove old hack for compiling with gcc-4.0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140573 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 22:30:57 +00:00
Owen Anderson
0afa0094af ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:06:22 +00:00
Jakob Stoklund Olesen
c291e2f578 Add target hook for pseudo instruction expansion. 
Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-25 19:21:35 +00:00
Craig Topper
4da632e6e0 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 06:57:25 +00:00
Andrew Trick
83a8031336 Restore hasPostISelHook tblgen flag. 
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 18:22:31 +00:00
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 03:17:40 +00:00
Eric Christopher
eae5a13078 Remove more of llvmc and dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:34:27 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:21:13 +00:00
David Greene
d9746fe58a Better Error Reporting 
Report missing template arguments more helpfully by supplying the name
of the missing argument in the error message.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 18:26:07 +00:00
Eric Christopher
04f138e225 Migrate this to use clang by default as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 20:36:22 +00:00
Eric Christopher
48dbeecd7e We now look for clang, then llvm-gcc, then gcc as our compiler. We don't need 
this anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139935 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 20:36:20 +00:00
Craig Topper
a08e255e1e Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 06:41:26 +00:00
Argyrios Kyrtzidis
516f52e24f [tablegen] In ClangAttrEmitter.cpp handle SourceLocation arguments to attributes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139617 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 18:41:43 +00:00
Argyrios Kyrtzidis
c9dccb8865 In ClangAttrEmitter.cpp emit code that allows attributes to keep their source range. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139598 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 16:05:43 +00:00
Craig Topper
58bbb81764 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 06:54:58 +00:00