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5 Commits

Author SHA1 Message Date
Craig Topper
07149fe715 Add patterns for converting stores of subvector_extracts of lower 128-bits of a 256-bit vector to VMOVAPSmr/VMOVUPSmr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163292 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 05:15:01 +00:00
Craig Topper
43e4c62c43 Commit test change for r162658. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162660 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-27 07:55:50 +00:00
Chad Rosier
1b1fdc0599 [avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to 
vextractf128 with 128-bit mem dest.

Combines

	vextractf128 $0, %ymm0, %xmm0
	vmovaps %xmm0, (%rdi)

to

    vextractf128 $0, %ymm0, (%rdi)

rdar://11082570


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153139 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 21:43:40 +00:00
Chad Rosier
36a273a76c [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove 
whitespace from test case.  No functional change intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 18:24:55 +00:00
Bruno Cardoso Lopes
ef8d6999f3 Add a dag combine to xform 256-bit shuffles into simple vector 
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137362 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:50:44 +00:00