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35f0febcb6
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186 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
35f0febcb6 Remove predicates when changing an add into an unpredicable mov. 
Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93909 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-19 21:08:28 +00:00
Bob Wilson
516ab96de3 Run the pre-register allocation tail duplication pass by default. Remove 
the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93597 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-16 00:29:50 +00:00
Jakob Stoklund Olesen
d1862037f0 Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-07 00:51:04 +00:00
Jakob Stoklund Olesen
30ac0467ce Add Target hook to duplicate machine instructions. 
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-06 23:47:07 +00:00
Dan Gohman
aceba31b7a Delete useless trailing semicolons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 17:55:26 +00:00
Nick Lewycky
0588bcef8d Make this test pass on Linux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 07:35:25 +00:00
Anton Korobeynikov
7cca606aaa Dynamic stack realignment use of sp register as source/dest register 
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90724 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-06 22:39:50 +00:00
Jim Grosbach
2a37b9c750 test case for IV-Users simplification loop improvement 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90260 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-01 21:53:51 +00:00
Evan Cheng
d7f0810c93 Enable predication of NEON instructions in Thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-24 08:06:15 +00:00
Jim Grosbach
77b02beb1f move fconst[sd] to UAL. <rdar://7414913> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 21:08:25 +00:00
Jim Grosbach
bbf56bb37b update test for 89694 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89695 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 20:39:53 +00:00
Edward O'Callaghan
18d18b71d5 Miss two, PR5307. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89596 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-22 15:35:28 +00:00
Edward O'Callaghan
f4a93dd70e Convert Thumb2 tests to FileCheck for PR5307. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89595 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-22 15:18:27 +00:00
Jim Grosbach
21ce2e3c74 Revert 89562. We're being sneakier than I was giving us credit for, and this 
isn't necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89568 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-21 23:34:09 +00:00
Jim Grosbach
f3b33d0b2a Darwin requires a frame pointer for all non-leaf functions to support correct 
backtraces.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89562 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-21 21:40:08 +00:00
Evan Cheng
c26abd9487 Enable hoisting load from constant memories. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89510 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 23:31:34 +00:00
Evan Cheng
4aedb61d03 Remat VLDRD from constpool. Clean up some instruction property specifications. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 19:57:15 +00:00
Evan Cheng
9b82425cb0 Also CSE non-pic load from constant pools. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89440 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-20 02:10:27 +00:00
Evan Cheng
2ef9c8a43d More consistent thumb1 asm printing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89328 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-19 06:57:41 +00:00
Evan Cheng
5b397c93a5 Shrink ldr / str [sp, imm0-1024] to 16-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89326 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-19 06:32:27 +00:00
Jim Grosbach
f04777b945 Enable arm jumpt table adjustment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89143 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 21:24:11 +00:00
Anton Korobeynikov
d2aad77261 Forgot to commit test fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89138 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 20:38:36 +00:00
Jim Grosbach
1187285e90 Convert to FileCheck 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89007 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 00:20:26 +00:00
Jim Grosbach
727f0c37fb Convert to FileCheck 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89002 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 00:03:38 +00:00
Jim Grosbach
2c0fb63738 Cleanup. Missed removing these when converting. Oops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89001 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 00:00:33 +00:00
Jim Grosbach
9f07f3b009 Convert to FileCheck 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88991 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-16 23:19:29 +00:00
Jim Grosbach
2f74603460 Convert to FileCheck 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88947 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-16 20:04:15 +00:00
Jim Grosbach
4adcade9b7 Convert to FileCheck 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88942 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-16 19:46:46 +00:00
Jim Grosbach
c0517504e5 tbb opt off by default 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88921 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-16 17:24:45 +00:00
Jim Grosbach
a44321776e Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-15 21:45:34 +00:00
Jim Grosbach
e11d26b3d8 remove xfail 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88817 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 21:57:35 +00:00
Evan Cheng
0cd22dd738 When expanding t2STRDi8 r, r to two stores, add kill markers correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88734 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 01:50:00 +00:00
Jim Grosbach
cb2c2b738a Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86997 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-12 17:19:09 +00:00
Benjamin Kramer
9e3728be62 Fix typo in run line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86984 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-12 12:35:27 +00:00
Evan Cheng
60f9061820 RegScavenger::enterBasicBlock should always reset register state. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86972 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-12 07:49:10 +00:00
Evan Cheng
586f69a118 - Teach LSR to avoid changing cmp iv stride if it will create an immediate that 
cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
  later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
  users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
  iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86969 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-12 07:35:05 +00:00
Dan Gohman
2210c0bea8 Add support for tail duplication to BranchFolding, and extend 
tail merging support to handle more cases.
 - Recognize several cases where tail merging is beneficial even when
   the tail size is smaller than the generic threshold.
 - Make use of MachineInstrDesc::isBarrier to help detect
   non-fallthrough blocks.
 - Check for and avoid disrupting fall-through edges in more cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86871 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-11 19:48:59 +00:00
Jim Grosbach
3f51147d44 Update test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86614 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 22:59:01 +00:00
Jim Grosbach
e5165490b7 Use Unified Assembly Syntax for the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 00:11:35 +00:00
Evan Cheng
d457e6e9a5 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 04:04:34 +00:00
Evan Cheng
78e5c1140a - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical 
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-07 03:52:02 +00:00
Evan Cheng
b9803a8fa6 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:52:48 +00:00
Bob Wilson
d51722a7e3 Fix a broken test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86298 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-06 23:06:42 +00:00
Evan Cheng
ad95ff9fab Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-04 00:42:33 +00:00
Evan Cheng
ba908640b3 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 05:52:54 +00:00
Anton Korobeynikov
7b360e7f29 Temporary xfail until PR5367 will be resolved 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85848 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-03 00:37:36 +00:00
Evan Cheng
7baae87d8f Unbreak ARMBaseRegisterInfo::copyRegToReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 04:44:55 +00:00
Evan Cheng
48d8afab73 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 21:12:51 +00:00
Evan Cheng
1107f03ef4 Fix tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85723 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 18:13:29 +00:00
Evan Cheng
de17fb6e4d Use cbz and cbnz instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85698 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 23:46:45 +00:00