21447 Commits

Author SHA1 Message Date
David Blaikie
4b1d68bca9 DebugInfo: Improve readability of test case added in r193878
The point is to ensure that the attribute in question
(DW_AT_data_member_location) is associated with the prior tag, so ensure
that we don't see another tag starting between the intended tag and the
desired attribute.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 20:59:53 +00:00
David Blaikie
84b418a997 DebugInfo: add a test case for data member locations (coverage for r193835)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193878 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 18:25:55 +00:00
David Blaikie
81d0b3c513 Fix a test case broken by r193872
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193876 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 18:18:16 +00:00
Manman Ren
cc14cb31d4 Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193874 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 18:06:25 +00:00
David Blaikie
2e110c3fa6 DebugInfo: Make pubnames header printing similar to unit header printing
In a failed attempt to allow the gnu-public-names.ll test case to not
hardcode the size of the unit that the pubnames section referred to I've
at least managed to have unit headers and pubnames headers print out in
a similar style.

This failed to achieve the desired goal because the header in a unit
specifies the length of the unit without the length element of the
header whereas the length in the pubnames includes this element, so the
numbers are off by 4 bytes. I don't know of any arithmetic powers in
FileCheck so the test case can't simply say "CU_LENGTH + 4".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 17:53:30 +00:00
Benjamin Kramer
7208b0763c LoopVectorize: Look for consecutive acces in GEPs with trailing zero indices
If we have a pointer to a single-element struct we can still build wide loads
and stores to it (if there is no padding).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193860 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 14:09:50 +00:00
Bradley Smith
6186de5c54 [ARM] Add Virtualization subtarget feature and more build attributes in this area
Add a Virtualization ARM subtarget feature along with adding proper build
attribute emission for Tag_Virtualization_use (encodes Virtualization and
TrustZone) and Tag_MPextension_use.

Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to
something that is more maintainable. This changes the focus of this
testcase away from testing CPU defaults (which is tested elsewhere), onto
specifically testing that attributes are encoded correctly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193859 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 13:27:35 +00:00
Bradley Smith
479a2de32a [ARM] Fix Tag_ABI_HardFP_use build attribute
Fix Tag_ABI_HardFP_use build attribute to handle single precision FP,
replace deprecated Tag_ABI_HardFP_use value of 3 with 0 and also add
some tests for Tag_ABI_VFP_args.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193856 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 11:21:16 +00:00
Hal Finkel
e14fb07357 Consider (x == -1) unlikely in BranchProbabilityInfo
This adds another heuristic to BPI, similar to the existing heuristic that
considers (x == 0) unlikely to be true. As suggested in the PACT'98 paper by
Deitrich, Cheng, and Hwu, -1 is often used to indicate an invalid index, and
equality comparisons with -1 are also unlikely to succeed. Local
experimentation supports this hypothesis: This yields a 1-2% speedup in the
test-suite sqlite benchmark on the PPC A2 core, with no significant
regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193855 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 10:58:22 +00:00
Arnold Schwaighofer
0097e15502 LoopVectorizer: If dependency checks fail try runtime checks
When a dependence check fails we can still try to vectorize loops with runtime
array bounds checks.

This helps linpack to vectorize a loop in dgefa. And we are back to 2x of the
scalar performance on a corei7-avx.

radar://15339680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193853 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 03:05:07 +00:00
Rafael Espindola
56ca8b3059 Use \01 to disable the mangler. Should fix the 32 bit windows bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193846 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 01:14:20 +00:00
David Blaikie
9b93392185 DebugInfo: Emit member variable locations as data instead of expressions in blocks
Drive by space optimization. Also makes the DIEs more regular which
might speed up DWARF parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193835 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 00:25:45 +00:00
Andrew Trick
6c4594f5b8 These test cases for experimental features are a bit too darwin-specific still. Use a triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:46:51 +00:00
Chad Rosier
1a035dd6df [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:36:59 +00:00
Andrew Trick
2ddc56dec8 Add new calling convention for WebKit Java Script.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193812 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:12:01 +00:00
Andrew Trick
3d74dea4bd Add support for stack map generation in the X86 backend.
Originally implemented by Lang Hames.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193811 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:11:56 +00:00
Rafael Espindola
53446e50a0 Relax check line to match what llvm-nm prints for COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193810 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:07:46 +00:00
Manman Ren
ef34496b3f Do not convert "call asm" to "invoke asm" in Inliner.
Given that backend does not handle "invoke asm" correctly ("invoke asm" will be
handled by SelectionDAGBuilder::visitInlineAsm, which does not have the right
setup for LPadToCallSiteMap) and we already made the assumption that inline asm
does not throw in InstCombiner::visitCallSite, we are going to make the same
assumption in Inliner to make sure we don't convert "call asm" to "invoke asm".

If it becomes necessary to add support for "invoke asm" later on, we will need
to modify the backend as well as remove the assumptions that inline asm does
not throw.

Fix rdar://15317907


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 21:56:03 +00:00
Rafael Espindola
fe0ae1db3a XFAIL on ppc64 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 21:27:02 +00:00
Rafael Espindola
6af049837a XFAIL this for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 21:22:43 +00:00
Rafael Espindola
7e667c56cf Use LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN instead of the "dso list".
There are two ways one could implement hiding of linkonce_odr symbols in LTO:
* LLVM tells the linker which symbols can be hidden if not used from native
  files.
* The linker tells LLVM which symbols are not used from other object files,
  but will be put in the dso symbol table if present.

GOLD's API is the second option. It was implemented almost 1:1 in llvm by
passing the list down to internalize.

LLVM already had partial support for the first option. It is also very similar
to how ld64 handles hiding these symbols when *not* doing LTO.

This patch then
* removes the APIs for the DSO list.
* marks LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN all linkonce_odr unnamed_addr
  global values and other linkonce_odr whose address is not used.
* makes the gold plugin responsible for handling the API mismatch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193800 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 20:51:58 +00:00
Chad Rosier
f7ba489730 [AArch64] Add diagnostic tests for NEON scalar shift immediate instructions (see: r193790).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 20:11:32 +00:00
Chad Rosier
1d28917dc3 [AArch64] Add support for NEON scalar shift immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 19:28:44 +00:00
Roman Divacky
1d6d49fbb1 SparcV9 doesnt have rem instruction either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193789 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 19:22:33 +00:00
Reid Kleckner
844e7d35d4 Use a larger invalid attribute bitcode number
That way the test won't start faililng when someone adds a new attribute
and wants to use the next logical enum (38) for bitcode.  The new
bitcode file tries to use the number 48 as an attribute instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193787 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 19:12:36 +00:00
Matt Arsenault
67b52144d2 Add FileCheck tests for @LINE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 18:18:09 +00:00
Petar Jovanovic
4999ae9cfa [mips] XFAIL several MCJIT remote tests
Two of the tests are new test cases (cross-module-a.ll, multi-module-a.ll)
not yet supported on MIPS, while XFAIL for the other two tests was
accidentally removed in r193570 and this change reverts those lines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193781 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 18:10:25 +00:00
Manman Ren
b8b70e10a2 Debug Info: remove duplication of DIEs when a DIE can be shared across CUs.
We add a map in DwarfDebug to map MDNodes that are shareable across CUs to the
corresponding DIEs: MDTypeNodeToDieMap. These DIEs can be shared across CUs,
that is why we keep the maps in DwarfDebug instead of CompileUnit.

We make the assumption that if a DIE is not added to an owner yet, we assume
it belongs to the current CU. Since DIEs for the type system are added to
their owners immediately after creation, and other DIEs belong to the current
CU, the assumption should be true.

A testing case is added to show that we only create a single DIE for a type
MDNode and we use ref_addr to refer to the type DIE.

We also add a testing case to show ref_addr relocations for non-darwin
platforms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 17:54:35 +00:00
Roman Divacky
6d6e66a3ee Merge and filecheckize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 17:50:45 +00:00
Andrew Trick
233012c25b Add Verifier test case for variable argument intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193768 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 17:18:17 +00:00
Andrew Trick
2e50b8a08d Enable variable arguments support for intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 17:18:11 +00:00
Cameron McInally
424f19732e Add AVX512 unmasked integer broadcast intrinsics and support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193748 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 13:56:31 +00:00
Elena Demikhovsky
f3280b5860 AVX-512: Implemented CMOV for 512-bit vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 13:15:32 +00:00
Richard Sandiford
793ce99ea7 [SystemZ] Automatically detect zEC12 and z196 hosts
As on other hosts, the CPU identification instruction is priveleged,
so we need to look through /proc/cpuinfo.  I copied the PowerPC way of
handling "generic".

Several tests were implicitly assuming z10 and so failed on z196.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 12:14:17 +00:00
Amara Emerson
c2884320fe [AArch64] Make the use of FP instructions optional, but enabled by default.
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 09:32:11 +00:00
NAKAMURA Takumi
0f5e68e3dc llvm/test/Bitcode/invalid.ll: Tweak expresion to mach "llvm-dis.EXE:"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193738 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 06:21:00 +00:00
Rafael Espindola
cc8c673e61 Fix a use after free on invalid input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 04:20:23 +00:00
Jim Grosbach
0e536ee4ca Legalize: Improve legalization of long vector extends.
When an extend more than doubles the size of the elements (e.g., a zext
from v16i8 to v16i32), the normal legalization method of splitting the
vectors will run into problems as by the time the destination vector is
legal, the source vector is illegal. The end result is the operation
often becoming scalarized, with the typical horrible performance. For
example, on x86_64, the simple input of:
define void @bar(<16 x i8> %a, <16 x i32>* %p) nounwind {
  %tmp = zext <16 x i8> %a to <16 x i32>
  store <16 x i32> %tmp, <16 x i32>*%p
  ret void
}

Generates:
  .section  __TEXT,__text,regular,pure_instructions
  .section  __TEXT,__const
  .align  5
LCPI0_0:
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .section  __TEXT,__text,regular,pure_instructions
  .globl  _bar
  .align  4, 0x90
_bar:
  vpunpckhbw  %xmm0, %xmm0, %xmm1
  vpunpckhwd  %xmm0, %xmm1, %xmm2
  vpmovzxwd %xmm1, %xmm1
  vinsertf128 $1, %xmm2, %ymm1, %ymm1
  vmovaps LCPI0_0(%rip), %ymm2
  vandps  %ymm2, %ymm1, %ymm1
  vpmovzxbw %xmm0, %xmm3
  vpunpckhwd  %xmm0, %xmm3, %xmm3
  vpmovzxbd %xmm0, %xmm0
  vinsertf128 $1, %xmm3, %ymm0, %ymm0
  vandps  %ymm2, %ymm0, %ymm0
  vmovaps %ymm0, (%rdi)
  vmovaps %ymm1, 32(%rdi)
  vzeroupper
  ret

So instead we can check if there are legal types that enable us to split
more cleverly when the input vector is already legal such that we don't
turn it into an illegal type. If the extend is such that it's more than
doubling the size of the input we check if
  - the number of vector elements is even,
  - the source type is legal,
  - the type of a split source is illegal,
  - the type of an extended (by doubling element size) source is legal, and
  - the type of that extended source when split is legal.
If the conditions are met, instead of just splitting both the
destination and the source types, we create an extend that only goes up
one "step" (doubling the element width), and the continue legalizing the
rest of the operation normally. The result is that this operates as a
new, more effecient, termination condition for the loop of "split the
operation until the destination type is legal."

With this change, the above example now compiles to:
_bar:
  vpxor %xmm1, %xmm1, %xmm1
  vpunpcklbw  %xmm1, %xmm0, %xmm2
  vpunpckhwd  %xmm1, %xmm2, %xmm3
  vpunpcklwd  %xmm1, %xmm2, %xmm2
  vinsertf128 $1, %xmm3, %ymm2, %ymm2
  vpunpckhbw  %xmm1, %xmm0, %xmm0
  vpunpckhwd  %xmm1, %xmm0, %xmm3
  vpunpcklwd  %xmm1, %xmm0, %xmm0
  vinsertf128 $1, %xmm3, %ymm0, %ymm0
  vmovaps %ymm0, 32(%rdi)
  vmovaps %ymm2, (%rdi)
  vzeroupper
  ret

This generalizes a custom lowering that was added a while back to the
ARM backend. That lowering is no longer necessary, and is removed. The
testcases for it, however, provide excellent ARM tests for this change
and so remain.

rdar://14735100

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193727 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 00:20:48 +00:00
Matt Arsenault
4f17f88071 Fix CodeGen for unaligned loads with address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 23:30:05 +00:00
Matt Arsenault
9effcbb879 Teach scalarrepl about address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193720 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 22:54:58 +00:00
Rafael Espindola
2cc546db18 Produce .weak_def_can_be_hidden for some linkonce_odr values
With this patch llvm produces a weak_def_can_be_hidden for linkonce_odr
if they are also unnamed_addr or don't have their address taken.

There is not a lot of documentation about .weak_def_can_be_hidden, but
from the old discussion about linkonce_odr_auto_hide and the name of
the directive this looks correct: these symbols can be hidden.

Testing this with the ld64 in Xcode 5 linking clang reduces the number of
exported symbols from 21053 to 19049.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193718 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 22:08:11 +00:00
Will Dietz
b7b1abef25 Add DebugInfo testcase for high_pc encoded as constant, fixed in r193555.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193711 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 20:27:17 +00:00
Matt Arsenault
b7ff48e374 Fix GVN creating bitcast between address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193710 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 19:05:41 +00:00
Tom Roeder
4ca9a2a0ad This commit adds some (but not all) of the x86-64 relocations that are not
currently supported in the ELF object writer, along with a simple test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193709 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 18:47:25 +00:00
Artyom Skrobov
3f04b50686 [ARM] NEON instructions were erroneously decoded from certain invalid encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 18:10:09 +00:00
Tom Stellard
aa1d078e7f R600: Custom lower f32 = uint_to_fp i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193701 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 17:22:05 +00:00
Daniel Sanders
02fbffd4e8 [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:45:42 +00:00
Daniel Sanders
c385709d83 [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics)
Also corrected the definition of the intrinsics for these instructions (the
result register is also the first operand), and added intrinsics for bsel and
bseli to clang (they already existed in the backend).

These four operations are mostly equivalent to bsel, and bseli (the difference
is which operand is tied to the result). As a result some of the tests changed
as described below.

bitwise.ll:
- bsel.v test adapted so that the mask is unknown at compile-time. This stops
  it emitting bmnzi.b instead of the intended bsel.v.
- The bseli.b test now tests the right thing. Namely the case when one of the
  values is an uimm8, rather than when the condition is a uimm8 (which is
  covered by bmnzi.b)

compare.ll:
- bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this
  is the same operation (see MSA.txt).

i8.ll
- CHECK-DAG-ized test.
- bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands
  because this is the same operation (see MSA.txt).
- bseli.b still emits bseli.b though because the immediate makes it
  distinguishable from bmnzi.b.

vec.ll:
- CHECK-DAG-ized test.
- bmz.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).
- bsel.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:20:38 +00:00
Chad Rosier
f853a034a1 [AArch64] Add support for NEON scalar floating-point compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:19:37 +00:00
Daniel Sanders
6ff1ef9931 [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 14:45:14 +00:00