153615 Commits

Author SHA1 Message Date
Eugene Zelenko
2de563a9ab [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311703 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 21:21:39 +00:00
Chad Rosier
ca52e12050 [PartialInlining] Formatting. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311702 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 21:21:09 +00:00
Nathan Hawes
71f4afc0b8 test commit: fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311701 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 21:20:41 +00:00
Chad Rosier
8209cdfb4c [PartialInlining] Type. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311699 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 20:29:02 +00:00
Konstantin Zhuravlyov
a698ffcfb3 AMDGPU: Fix gfx801 features
gfx801 has 1/2 rate F64, Fast F32 FMA

Differential Revision: https://reviews.llvm.org/D36981


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311694 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 20:03:07 +00:00
Jacob Gravelle
73e192592e [WebAssembly] FastISel : Bail to SelectionDAG for constexpr calls
Summary: Currently FastISel lowers constexpr calls as indirect calls.
We'd like those to direct calls, and falling back to SelectionDAGISel
handles that.

Reviewers: dschuff, sunfish

Subscribers: jfb, sbc100, llvm-commits, aheejin

Differential Revision: https://reviews.llvm.org/D37073

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311693 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 19:53:44 +00:00
Heejin Ahn
3133c0dc5b [WebAssembly] Update GCC test suite failure expectations
Summary:
Update GCC test suite failure expectations as we add -O0 to the bare tests in
WebAssembly waterfall. There are still several untriaged lld failures.

Reviewers: sbc100, jgravelle-google, dschuff

Reviewed By: dschuff

Subscribers: jfb

Differential Revision: https://reviews.llvm.org/D37100

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311691 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 19:43:09 +00:00
Krzysztof Parzyszek
c20cb18c00 [Hexagon] Set access size for vector pseudo loads/stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311690 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 19:19:24 +00:00
Daniel Sanders
a8273d0212 [globalisel][tablegen] Predicates should start from GIPFP_Invalid+1 not GIPFP_Invalid
This fixes a warning when there are zero defined predicates and also fixes an
unnoticed bug where the first predicate in the table was unusable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311684 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 18:54:16 +00:00
Victor Leschuk
e34366cdd6 Remove duplicate code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311675 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 17:02:38 +00:00
Victor Leschuk
b9f31ca1b8 Add missing break in switch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311673 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 16:57:10 +00:00
Pete Couperus
53355ce574 [ARC] Add ARC backend.
Add the ARC backend as an experimental target to lib/Target.
Reviewed at: https://reviews.llvm.org/D36331



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311667 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 15:40:33 +00:00
Krasimir Georgiev
f372a9f69a [X86AsmParser] Refactor AsmRewrite constructors, NFCI
Summary:
This is a follow-up of https://reviews.llvm.org/D37105, where a slight refactoring
of the constructors of AsmRewrite is proposed.

Reviewers: coby

Reviewed By: coby

Differential Revision: https://reviews.llvm.org/D37110

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311666 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 15:03:18 +00:00
Sanjay Patel
616b6cc126 fix typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 15:00:13 +00:00
Sjoerd Meijer
bfcfe1e763 [AArch64] Add FMOVH0: materialize 0 using zero register for f16 values
Instead of loading 0 from a constant pool, it's of course much better to
materialize it using an fmov and the zero register.

Thanks to Ahmed Bougacha for the suggestion.

Differential Revision: https://reviews.llvm.org/D37102


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311662 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 14:47:06 +00:00
Sanjay Patel
e8714301ce [BypassSlowDivision] move map helper code to header; NFC
We can reuse this code with other div/rem transforms as shown in:
https://reviews.llvm.org/D31037 
https://bugs.llvm.org/show_bug.cgi?id=31028


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311661 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 14:43:33 +00:00
Chad Rosier
b142bc0a90 [TargetParser][AArch64] Add support for RDM feature in the target parser.
Differential Revision: https://reviews.llvm.org/D37081

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311659 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 14:30:44 +00:00
Michael Zuckerman
9db416111e Adding base lit test for x86interleaved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311658 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 14:11:28 +00:00
Coby Tayree
7037942461 [fixup][rL311639]
rL311639 created X86AsmParser a dependency in X86AsmPrinter, which broke builds
this fix adds the necessary dep



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311657 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 14:10:50 +00:00
Krasimir Georgiev
a6a165e0a8 [X86AsmParser] Fix msan: use-of-uninitialized-value after r311639
Summary:
CodeGen/ms-inline-asm.c test triggers msan use-of-uninitialized-value here:
llvm/lib/MC/MCParser/AsmParser.cpp:5629:7

Reviewers: bkramer, coby

Differential Revision: https://reviews.llvm.org/D37105

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311653 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 13:38:18 +00:00
Krzysztof Parzyszek
3dfcd099f5 [Hexagon] Generate correct runtime check when recognizing memmove
The check (assuming positive stride) for validity of memmove should be
(a) the destination is at a lower address than the source, or
(b) the distance between the source and destination is greater than or
    equal the number of bytes copied.

For the second part it is sufficient to assume that the destination
is at a higher address, since the opposite case is covered by (a).
The distance calculation was previously done by subtracting the
pointers in the wrong order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311650 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 11:59:53 +00:00
Evgeny Astigeevich
6e59618ef9 [ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting illegal modes
ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes
for the Thumb1 target. This causes generation of redundant code and affects
performance.

This fixes PR34106: https://bugs.llvm.org/show_bug.cgi?id=34106

Differential Revision: https://reviews.llvm.org/D36467


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311649 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 10:00:25 +00:00
Tobias Grosser
2050a0312d Model cache size and associativity in TargetTransformInfo
Summary:
We add the precise cache sizes and associativity for the following Intel
architectures:

  - Penry
  - Nehalem
  - Westmere
  - Sandy Bridge
  - Ivy Bridge
  - Haswell
  - Broadwell
  - Skylake
  - Kabylake

Polly uses since several months a performance model for BLAS computations that
derives optimal cache and register tile sizes from cache and latency
information (based on ideas from "Analytical Modeling Is Enough for High-Performance BLIS", by Tze Meng Low published at TOMS 2016).
While bootstrapping this model, these target values have been kept in Polly.
However, as our implementation is now rather mature, it seems time to teach
LLVM itself about cache sizes.

Interestingly, L1 and L2 cache sizes are pretty constant across
micro-architectures, hence a set of architecture specific default values
seems like a good start. They can be expanded to more target specific values,
in case certain newer architectures require different values. For now a set
of Intel architectures are provided.

Just as a little teaser, for a simple gemm kernel this model allows us to
improve performance from 1.2s to 0.27s. For gemm kernels with less optimal
memory layouts even larger speedups can be reported.

Reviewers: Meinersbur, bollu, singam-sanjay, hfinkel, gareevroman, fhahn, sebpop, efriedma, asb

Reviewed By: fhahn, asb

Subscribers: lsaba, asb, pollydev, llvm-commits

Differential Revision: https://reviews.llvm.org/D37051

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311647 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 09:46:25 +00:00
Sjoerd Meijer
9a6d31e0ca [AArch64] Custom lowering of copysign f16
This is a follow up patch of r311154 and introduces custom lowering of copysign
f16 to avoid promotions to single precision types when the subtarget supports
fullfp16.

Differential Revision: https://reviews.llvm.org/D36893


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311646 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 09:21:10 +00:00
Daniel Sanders
02ad65f1a0 Re-commit: [globalisel][tablegen] Add support for ImmLeaf without SDNodeXForm
Summary:
This patch adds support for predicates on imm nodes but only for ImmLeaf and not
for PatLeaf or PatFrag and only where the value does not need to be transformed
before being rendered into the instruction.

The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the
necessary target-supplied C++ for GlobalISel.

Depends on D36085

The previous commit was reverted for breaking the build but this appears to have
been the recurring problem on the Windows bots with tablegen not being re-run
when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a
build with clean=True should fix it but this string should do this in advance:
    Requires a clean build.

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: rovka

Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D36086



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311645 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 09:11:20 +00:00
Coby Tayree
67d905be8e [LLVM][x86][Inline Asm] support for GCC style inline asm - Y<x> constraints
This patch is intended to enable the use of basic double letter constraints used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}.
Supersedes D35204
Clang counterpart: D36371

Differential Revision: https://reviews.llvm.org/D36369


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311644 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 09:08:33 +00:00
Mikael Holmen
6dbfbe1563 [Reassociate] Do not drop debug location if replacement is missing
Summary:
When reassociating an expression, do not drop the instruction's
original debug location in case the replacement location is
missing.

The debug location must at least not be dropped for inlinable
callsites of debug-info-bearing functions in debug-info-bearing
functions. Failing to do so would result in an "inlinable function "
"call in a function with debug info must have a !dbg location"
error in the verifier.

As preserving the original debug location is not expected
to result in overly jumpy debug line information, it is
preserved for all other cases too.

This fixes PR34231:
https://bugs.llvm.org/show_bug.cgi?id=34231

Original patch by David Stenberg

Reviewers: davide, craig.topper, mcrosier, dblaikie, aprantl

Reviewed By: davide, aprantl

Subscribers: aprantl

Differential Revision: https://reviews.llvm.org/D36865

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311642 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 09:05:00 +00:00
Coby Tayree
89feab7412 [X86AsmParser] Refactoring, (almost) NFC.
Some refactoring to X86AsmParser, mostly regarding the way rewrites are conducted.
Mainly, we try to concentrate all the rewrite effort under one hood, so it'll hopefully be less of a mess and easier to maintain and understand.
naturally, some frontend tests were affected: D36794

Differential Revision: https://reviews.llvm.org/D36793


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311639 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 08:46:25 +00:00
Matt Arsenault
1a6aed20fa IPRA: Don't assume called function is first call operand
Fixes not finding the called global for AMDGPU
call pseudoinstructions, which prevented IPRA
from doing much.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311637 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 07:55:15 +00:00
Matt Arsenault
ee106fcc4b IPRA: Exit early on functions without calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311636 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 07:55:13 +00:00
Sjoerd Meijer
4dc1f84c31 [AArch64] fix for fcos and frem f16 promotion
Fix for copy-paste mistake in r311154; setOperationAction for fcos and frem f16
operands appeared twice (and it should be set to 'promote').

Differential Revision: https://reviews.llvm.org/D37071



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311635 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 07:43:52 +00:00
Chandler Carruth
ea64a39482 [x86] NFC: Clean up two tests and generate precise checks for them.
Mostly this involved giving unnamed values names and running the IR
through `opt` to re-format it but merging in any important comments in
the original. I then deleted pointless comments and inlined the function
attributes for ease of reading and editting.

All of this is to make it much easier to see the instructions being
generated here and evaluate any updates to the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311634 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 07:38:36 +00:00
Igor Breger
5b46835851 [GlobalISel][X86] Support G_IMPLICIT_DEF.
Summary: Support G_IMPLICIT_DEF.

Reviewers: zvi, guyblank, t.p.northover

Reviewed By: guyblank

Subscribers: rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D36733

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311633 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 07:06:27 +00:00
Lang Hames
5a19c2915c [docs] In the CMake primer, correct the description of the ARGV/ARGN variables.
ARGN is the sublist of unnamed arguments, not the count of the arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311632 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 05:38:39 +00:00
Lang Hames
a69b2ae909 [Support] Rewrite handleAllErrors in terms of cantFail.
This just switches handleAllErrors from using custom assertions that all errors
have been handled to using cantFail. This change involves moving some of the
class and function definitions around though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311631 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 05:35:27 +00:00
Wei Ding
75acc65cb3 Add ‘llvm.experimental.constrained.fma‘ Intrinsic.
Differential Revision: http://reviews.llvm.org/D36335

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311629 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 04:18:24 +00:00
Adam Nemet
05f89d64f5 Support all integer types in DiagnosticInfoOptimizationBase::Argument
We were missing size_t (unsigned long) on macOS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311628 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 04:04:49 +00:00
Daniel Berlin
9dc6eddb1d NewGVN: We weren't properly simplifying selects with equal arguments due to a thinko.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311626 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 02:43:17 +00:00
Eric Beckmann
e90e727e0d Fix bug 34051 by handling empty .res files gracefully.
Summary:
Previously, llvm-cvtres crashes on .res files which are empty except for
the null header.  This allows the library to simply pass over them.

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D37044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311625 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 02:36:50 +00:00
Hans Wennborg
6d2214fde6 [DAG] Fix Node Replacement in PromoteIntBinOp
When one operand is a user of another in a promoted binary operation
we may replace and delete the returned value before returning
triggering an assertion. Reorder node replacements to prevent this.

Fixes PR34137.

Landing on behalf of Nirav.

Differential Revision: https://reviews.llvm.org/D36581

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311623 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 01:08:27 +00:00
Dylan McKay
e42da35bfc [AVR] Use the correct register classes for 16-bit atomic operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311620 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 00:14:38 +00:00
Dehao Chen
4d101c0667 Add test to cover accurate-sample-profile.
Summary: This patch adds test to cover the logic guarded by "accurate-sample-profile" flag.

Reviewers: davidxl

Reviewed By: davidxl

Subscribers: sanjoy, llvm-commits, eraman

Differential Revision: https://reviews.llvm.org/D37084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311618 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-23 23:19:11 +00:00
Tim Northover
b97dac5226 ARM: use internal relocations for local symbols after all.
Switching to external relocations for ARM-mode branches (to allow Thumb
interworking when the offset is unencodable) causes calls to temporary symbols
to be miscompiled and instead go to the parent externally visible symbol.

Calling a temporary never happens in compiled code, but can occasionally in
hand-written assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311611 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-23 22:07:10 +00:00
Adrian Prantl
91ad652cd8 Retire the llvm.dbg.mir hack after r311594.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311610 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-23 22:02:36 +00:00
Aditya Nandakumar
8bb11e0e80 Fix Verifier test - add REQUIRES aarch64-registered-target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311609 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-23 21:55:36 +00:00
Adrian Prantl
a2224c91e5 Add a Verifier check for DILocation's scopes.
Found via https://bugs.llvm.org/show_bug.cgi?id=33997.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311608 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-23 21:52:24 +00:00
Jonas Devlieghere
e69aa182b7 [WebAssembly] Fix overflow for input with missing version
Differential revision: https://reviews.llvm.org/D37070

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311605 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-23 21:36:04 +00:00
Rong Xu
7996242b16 [PGO] Set edge weights for indirectbr instruction with profile counts
Current PGO only annotates the edge weight for branch and switch instructions
with profile counts. We should also annotate the indirectbr instruction as
all the information is there. This patch enables the annotating for indirectbr
instructions. Also uses this annotation in branch probability analysis.

Differential Revision: https://reviews.llvm.org/D37074


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311604 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-23 21:36:02 +00:00
Geoff Berry
78d28dbc5a [AArch64][Falkor] Fix bug in Falkor HWPF tag collision avoidance
LDPDi was incorrectly marked as ignoring the destination register in the
prefetcher tag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311599 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-23 21:11:28 +00:00
Pete Couperus
333b7c6706 Test commit.
Fix instrinsic -> intrinsic typo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311598 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-23 20:58:22 +00:00