136 Commits

Author SHA1 Message Date
Strahinja Petrovic
75d0a5b667 [Mips] Emit the correct DINS variant
This patch fixes emitting of correct variant of DINS instruction.

Differential Revision: https://reviews.llvm.org/D30988


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298596 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-23 13:40:07 +00:00
Eugene Zelenko
c7e2e47b27 [Mips] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293729 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-01 01:22:51 +00:00
Hrvoje Varga
00748f49d4 [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations
Differential Revision: https://reviews.llvm.org/D22667


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279429 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-22 12:17:59 +00:00
Daniel Sanders
7dd6fd6b28 Re-commit r277988: [mips][ias] Fix all the hacks related to MIPS-specific unary operators (%hi/%lo/%gp_rel/etc.).
Hopefully with the MSVC builds fixed. I've added a missing '#include <tuple>'
that gcc and clang don't seem to need.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277995 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-08 11:50:25 +00:00
Daniel Sanders
0985f50be7 Revert r277988: [mips][ias] Fix all the hacks related to MIPS-specific unary operators (%hi/%lo/%gp_rel/etc.).
It seems that MSVC doesn't like std::tie().



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277990 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-08 09:33:14 +00:00
Daniel Sanders
007417372d [mips][ias] Fix all the hacks related to MIPS-specific unary operators (%hi/%lo/%gp_rel/etc.).
Summary:
They are now lexed as a single token on targets where
MCAsmInfo::HasMipsExpressions is true and then parsed in a similar way to
the '~' operator as part of MCExpr::parseExpression.

As a result:
* expressions and immediates no longer have different parsing rules. The
  difference is now solely down to whether evaluateAsAbsolute() succeeds.
* %hi(%neg(%gp_rel(x))) are no longer parsed as a single operator and
  decomposed into the three MipsMCExpr nodes. They are parsed directly as
  three MipsMCExpr nodes.
  * parseMemOperand no longer needs to eat all the surrounding parenthesis
    to get at the outermost operator to make this work
* %hi(%neg(%gp_rel(x))) and %lo(%neg(%gp_rel(x))) are no longer the only
  3-in-1 relocs that parse for N64. They're still the only combinations that
  are permitted in relocatable expressions though. Fixing that should be a
  later patch.
* We no longer need to list all the tokens that can occur as the first token of
  an expression or immediate.

test/MC/Mips/expr1.s:
    This change also prevents the incorrect lowering of %lo(2*4)+foo to
    %lo(8+foo) which is not an equivalent expression (the difference is
    whether foo is truncated to 16-bit or not) and the test has been
    updated to account for the macro expansion the correct expression requires.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D23110

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277988 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-08 09:20:52 +00:00
Simon Dardis
edf7e07438 [mips] MIPS64R6 compact branch support
MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct
MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that
map to the same instruction, extend compact branch support for the
corresponding 64bit branches.

Reviewers: dsanders

Differential Revision: https://reviews.llvm.org/D20164


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276739 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-26 10:25:07 +00:00
Zlatko Buljan
279cd1ed0b [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support
Differential Revision: http://reviews.llvm.org/D18824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275050 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-11 07:41:56 +00:00
Hrvoje Varga
b256e8a5b2 [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions
Differential Revision: http://reviews.llvm.org/D16625


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273850 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-27 08:23:28 +00:00
Hrvoje Varga
98d31c1b79 [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions
Differential Revision: http://reviews.llvm.org/D16917


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272876 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-16 07:06:25 +00:00
Hrvoje Varga
221d208604 [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions
Differential Revision: http://reviews.llvm.org/D11798


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272259 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-09 12:57:23 +00:00
Simon Dardis
f213957c14 [mips] Enforce compact branch register restrictions
Enforce compact branch register restrictions such as the use of the zero
register, both operands being the same register. Emit clear error in such
cases as the issue is subtle.

For bovc and bnvc, silently fixup such cases when emitting objects directly,
like LLVM started doing in rL269899.

Reviewers: vkalintiris, dsanders

Differential Review: http://reviews.llvm.org/D20475


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271301 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 17:34:42 +00:00
Zoran Jovanovic
785d7f7fbf ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocation
Differential Revision: http://reviews.llvm.org/D15526


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270048 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-19 12:20:40 +00:00
Simon Dardis
2366631516 [PATCH] [mips] Restrict the creation of compact branches
Restrict the creation of compact branches so that they do meet the ISA
requirements. Notably do not permit $zero to be used as a operand for compact
branches and ensure that some other branches fulfil the requirement that
rs != rt.

Fixup cases where $rs > $rt for bnec and beqc.

Recommit of rL269893 with reviewers comments.

Reviewers: dsanders, vkalintiris

Differential Review: http://reviews.llvm.org/D20284



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269899 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-18 10:38:01 +00:00
Simon Dardis
c0a6ad42eb Revert "[mips] Restrict the creation of compact branches"
This reverts commit rL269893.

Incorrect patch applied.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269897 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-18 09:51:37 +00:00
Simon Dardis
79149b9fae [mips] Restrict the creation of compact branches
Restrict the creation of compact branches so that they meet the ISA encoding
requirements. Notably do not permit $zero to be used as a operand for compact
branches and ensure that some other branches fulfil the requirement that
rs != rt.

Fixup cases where $rs > $rt for bnec and beqc.

Reviewers: dsanders, vkalintiris

Differential Review: http://reviews.llvm.org/D20284


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269893 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-18 09:21:44 +00:00
Zoran Jovanovic
9027d962e1 [mips][microMIPS] Implement BEQZC and BNEZC instructions
Differential Revision: http://reviews.llvm.org/D15417


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269755 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-17 11:10:15 +00:00
Hrvoje Varga
2d6c428cea [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions
Differential Revision: http://reviews.llvm.org/D14117


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269408 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 11:32:53 +00:00
Hrvoje Varga
6c8d6522ab Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"
This reverts commit r269176 as it caused test-suite failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269287 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 12:46:06 +00:00
Hrvoje Varga
eef2fa80b4 [mips][microMIPS] Implement CFC*, CTC* and LDC* instructions
Differential Revision: http://reviews.llvm.org/D19713


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269176 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-11 12:12:24 +00:00
Daniel Sanders
c8b0a11468 [mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations.
Summary:
This is much closer to the way MIPS relocation expressions work
(%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the
various bodges in MipsAsmParser::evaluateRelocExpr().

Removing those bodges ensures that the constant stored in MCValue is the
full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used
to correct the %hi/%lo matching needed to sort the relocation table correctly.

As part of this:
* Gave MCExpr::print() the ability to omit parenthesis when emitting a
  symbol reference inside a MipsMCExpr operator like %hi(X). Without this
  we print things like %lo(($L1)).
* %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of
  the related special cases have been removed or moved to MipsMCExpr. We
  can remove the rest as we gain support for the less common relocations
  when they are not part of this specific combination.
* Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion
  with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_').
* fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical
  and merged into fixup_Mips_GOT.
* MO_GOT16 and MO_GOT turned out to be identical and have been merged into
  MO_GOT.
* VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they
  have been merged into MEK_GOT

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19716


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268379 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-03 13:35:44 +00:00
Zoran Jovanovic
762ad97089 [mips][microMIPS] Revert commit r266861.
Commit r266861 was the reason for failing tests in LLVM test suite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267166 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 16:53:15 +00:00
Zoran Jovanovic
c1499f8232 [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocation
Differential Revision: http://reviews.llvm.org/D15026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267130 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 10:15:12 +00:00
Zoran Jovanovic
161372b940 [mips][microMIPS] Add R_MICROMIPS_PC19_S2 relocation
Differential Revision: http://reviews.llvm.org/D14915


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266988 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 14:09:35 +00:00
Zoran Jovanovic
ddc504898c [mips][microMIPS] Add R_MICROMIPS_PC26_S1 relocation
Differential Revision: http://reviews.llvm.org/D14822


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266985 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 13:43:26 +00:00
Hrvoje Varga
6ae2468651 [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions
Differential Revision: http://reviews.llvm.org/D18640


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266861 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-20 06:34:48 +00:00
Daniel Sanders
2693fe3c51 [mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]
Summary:
Also, made test_mi10.s formatting consistent with the majority of the
MC tests.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18435


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265014 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-31 14:12:01 +00:00
Daniel Sanders
0178becd87 [mips] Make isel select the correct DEXT variant up front.
Summary:
Previously, it would always select DEXT and substitute any invalid matches
for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works
but causes problems when adding range checked immediates to IAS.

Now isel selects the correct variant up front.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D16810

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262229 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-29 15:26:54 +00:00
Zlatko Buljan
ba4a99ac26 [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions
Differential Revision: http://reviews.llvm.org/D15570


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256152 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21 13:08:58 +00:00
Zoran Jovanovic
b294a7b51a [mips][microMIPS] Fix issue with offset operand of BALC and BC instructions
Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit.
Differential Revision: http://reviews.llvm.org/D14770


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254296 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-30 12:56:18 +00:00
Zlatko Buljan
567a66317d [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions
Differential Revision: http://reviews.llvm.org/D11406


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252885 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-12 13:21:33 +00:00
Daniel Sanders
f5ed626e96 [mips][ias] Range check uimm2 operands and fix a bug this revealed.
Summary:
The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA
(unlike the MSA version) failed to account for the off-by-one encoding of the
immediate. The range is actually 1..4 rather than 0..3.

Reviewers: vkalintiris

Subscribers: atanasyan, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D14015


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252295 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-06 12:22:31 +00:00
Hrvoje Varga
bf6106bf51 [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions
Differential Revision: http://reviews.llvm.org/D11633


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250511 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-16 12:24:58 +00:00
Zoran Jovanovic
c6d9c4ee81 [mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation
Differential Revision: http://reviews.llvm.org/D12798


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250058 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-12 16:07:25 +00:00
Zoran Jovanovic
1b6640a5fc [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6
Differential Revision: http://reviews.llvm.org/D11632


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247670 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 10:05:10 +00:00
Zoran Jovanovic
3acfef5bd3 [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions
Differential Revision: http://reviews.llvm.org/D11801


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246999 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-08 10:18:38 +00:00
Zoran Jovanovic
0697651ac5 [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions
Differential Revision: http://reviews.llvm.org/D10956


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246987 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-08 08:25:34 +00:00
Petar Jovanovic
7c5bf4d38a [mips64] Emit correct addend for some PC-relative relocations
So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch
fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation.

Patch by Vladimir Radosavljevic.

Differential Revision: http://reviews.llvm.org/D10565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240404 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-23 13:54:42 +00:00
Jim Grosbach
586c0042da MC: Clean up MCExpr naming. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238634 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-30 01:25:56 +00:00
Michael Kuperstein
d714fcf5c8 Use std::bitset for SubtargetFeatures.
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures.
Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. 
This should now be fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238192 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-26 10:47:10 +00:00
Pete Cooper
39aa893201 Remove 3 includes from MCInstrDesc.h and explicitly include them where needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237481 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-15 21:58:42 +00:00
Jim Grosbach
251a66ec37 MC: Update MCCodeEmitter naming. NFC.
s/EncodeInstruction/encodeInstruction/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237469 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-15 19:13:16 +00:00
Jim Grosbach
8b22e9c00a MC: Update MCFixup naming. NFC.
s/MCFixup::Create/MCFixup::create/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237468 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-15 19:13:05 +00:00
Michael Kuperstein
66112dd7f8 Reverting r237234, "Use std::bitset for SubtargetFeatures"
The buildbots are still not satisfied.
MIPS and ARM are failing (even though at least MIPS was expected to pass).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237245 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-13 10:28:46 +00:00
Michael Kuperstein
1336daad86 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first two times this was committed (r229831, r233055), it caused several buildbot failures. 
At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237234 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-13 08:27:08 +00:00
Zoran Jovanovic
d311051513 [mips][microMIPSr6] Implement mips32 to microMIPSr6 mapping support
Differential Revision: http://reviews.llvm.org/D8661


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235505 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-22 13:27:34 +00:00
Jozef Kolek
7ab9941632 [mips][microMIPSr6] Implement initial mapping support
Differential Revision: http://reviews.llvm.org/D8387


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235298 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 12:42:08 +00:00
Jozef Kolek
ec47ed84d2 [mips][microMIPSr6] Implement initial subtarget support
Differential Revision: http://reviews.llvm.org/D8386


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235296 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 12:23:06 +00:00
Michael Kuperstein
765aab84d6 Revert "Use std::bitset for SubtargetFeatures"
This reverts commit r233055.

It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233068 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 12:56:59 +00:00
Michael Kuperstein
d3ab717935 Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first time this was committed (r229831), it caused several buildbot failures. 
At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed.

Differential Revision: http://reviews.llvm.org/D8542

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233055 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-24 09:17:25 +00:00