RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-05-23 05:46:05 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
147,497 Commits 39 Branches 10 Tags
Commit Graph

8 Commits

Author SHA1 Message Date
Alex Bradbury
ff1254b6f8 Add MCContext argument to MCAsmBackend::applyFixup for error reporting 
A number of backends (AArch64, MIPS, ARM) have been using
MCContext::reportError to report issues such as out-of-range fixup values in
their TgtAsmBackend. This is great, but because MCContext couldn't easily be
threaded through to the adjustFixupValue helper function from its usual
callsite (applyFixup), these backends ended up adding an MCContext* argument
and adding another call to applyFixup to processFixupValue. Adding an
MCContext parameter to applyFixup makes this unnecessary, and even better -
applyFixup can take a reference to MCContext rather than a potentially null
pointer.

Differential Revision: https://reviews.llvm.org/D30264


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299529 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-04-05 10:16:14 +00:00
Alex Bradbury
6eaf72c16b [RISCV] Fix RV32 datalayout string and ensure initAsmInfo is called 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295028 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-14 05:20:20 +00:00
Alex Bradbury
0f17e9df2d [RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295027 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-14 05:17:23 +00:00
Alex Bradbury
81a8ce81a8 [RISCV] Fix unused variable in RISCVMCTargetDesc. NFC 
Also, for better uniformity use TargetRegistry::RegisterMCAsmInfo rather than 
RegisterMCAsmInfoFn. Again, no functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295026 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-14 05:15:24 +00:00
Aaron Ballman
41b84edffa Removing a switch statement that contains a default label, but no case labels. Silences an MSVC warning; NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285806 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-02 13:58:57 +00:00
Alex Bradbury
5ded6ebfad [RISCV] Add bare-bones RISC-V MCTargetDesc 
This is enough to compile and link but doesn't yet do anything particularly 
useful. Once an ASM parser and printer are added in the next two patches, the 
whole thing can be usefully tested.

Differential Revision: https://reviews.llvm.org/D23562


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285770 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-01 23:47:30 +00:00
Alex Bradbury
72d5de4e70 [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td 
For now, only add instruction definitions for basic ALU operations. Our 
initial target is a working MC layer rather than codegen, so appropriate 
SelectionDAG patterns will come later.

Differential Revision: https://reviews.llvm.org/D23561


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285769 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-01 23:40:28 +00:00
Alex Bradbury
0ba26af40d [RISCV] Add stub backend 
This contains just enough for lib/Target/RISCV to compile. Notably a basic 
RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc 
-march=riscv32 myinput.ll and will find it fails due to the lack of 
MCAsmInfo.

See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for 
further discussion

Differential Revision: https://reviews.llvm.org/D23560


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285712 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-01 17:27:54 +00:00