3 Commits

Author SHA1 Message Date
Jun Bum Lim
232aafceb5 [MachineScheduler]Add support for store clustering
Perform store clustering just like load clustering. This change add
StoreClusterMutation in machine-scheduler. To control StoreClusterMutation,
added enableClusterStores() in TargetInstrInfo.h. This is enabled only on
AArch64 for now.

This change also add support for unscaled stores which were not handled in
getMemOpBaseRegImmOfs().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266437 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-15 14:58:38 +00:00
Evandro Menezes
891346a0b1 [AArch64] Disable LDP/STP for quads
Disable LDP/STP for quads on Exynos M1 as they are not as efficient as pairs
of regular LDR/STR.

Patch by Abderrazek Zaafrani <a.zaafrani@samsung.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266223 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 18:31:45 +00:00
Chad Rosier
b0c326b0a1 [AArch64] Enable more load clustering in the MI Scheduler.
This patch adds unscaled loads and sign-extend loads to the TII
getMemOpBaseRegImmOfs API, which is used to control clustering in the MI
scheduler. This is done to create more opportunities for load pairing.  I've
also added the scaled LDRSWui instruction, which was missing from the scaled
instructions. Finally, I've added support in shouldClusterLoads for clustering
adjacent sext and zext loads that too can be paired by the load/store optimizer.

Differential Revision: http://reviews.llvm.org/D18048

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263819 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-18 19:21:02 +00:00