5 Commits

Author	SHA1	Message	Date
Luis Marques	85abf858b2	[RISCV] Switch to the Machine Scheduler ... Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372106 91177308-0d34-0410-b5e6-96231b3b80d8	2019-09-17 11:15:35 +00:00
Luis Marques	3049bc0fef	Revert Patch from Phabricator ... This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372104 91177308-0d34-0410-b5e6-96231b3b80d8	2019-09-17 10:52:09 +00:00
Luis Marques	955b80686a	Patch from Phabricator ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372092 91177308-0d34-0410-b5e6-96231b3b80d8	2019-09-17 09:43:08 +00:00
Alex Bradbury	5816be49d6	[RISCV] Add RV64F codegen support ... This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352807 91177308-0d34-0410-b5e6-96231b3b80d8	2019-01-31 22:48:38 +00:00
Alex Bradbury	a07f460d52	[RISCV] Add codegen for RV32F arithmetic and conversion operations ... Currently, only a soft floating point ABI is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327976 91177308-0d34-0410-b5e6-96231b3b80d8	2018-03-20 12:45:35 +00:00