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60e32b0776
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6452 Commits

Author SHA1 Message Date
Chris Lattner
60e32b0776 Fit in 80-cols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30556 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-21 05:46:00 +00:00
Nick Lewycky
70084fd53a Fix compile error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30553 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-21 02:08:31 +00:00
Anton Korobeynikov
f824868ed9 Adding codegeneration for StdCall & FastCall calling conventions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30549 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 22:03:51 +00:00
Andrew Lenharth
c459bbf0fd Account for pseudo-ops correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30548 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 20:08:52 +00:00
Chris Lattner
4da1c82f72 The DarwinAsmPrinter need not check for isDarwin. createPPCAsmPrinterPass 
should create the right asmprinter subclass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30542 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 17:12:19 +00:00
Chris Lattner
dadceedbdb Wrap some darwin'isms with isDarwin checks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30541 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 17:07:15 +00:00
Andrew Lenharth
6b634037b3 catch constants more often 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30534 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 15:05:49 +00:00
Andrew Lenharth
886f98e6f9 clarify with test case 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30531 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 14:48:00 +00:00
Andrew Lenharth
0b78f3e4b4 Add Note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30530 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 14:40:01 +00:00
Chris Lattner
f142713a30 item done 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30518 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 06:41:56 +00:00
Chris Lattner
7e932de7f5 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30515 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 06:32:10 +00:00
Chris Lattner
ac924c8248 This is already done 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30512 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 04:59:33 +00:00
Chris Lattner
711762497c Improve PPC64 equality comparisons like PPC32 comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30510 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 04:33:27 +00:00
Chris Lattner
3836dbd3bd Two improvements: 
1. Codegen this comparison:
     if (X == 0x8000)

as:

        cmplwi cr0, r3, 32768
        bne cr0, LBB1_2 ;cond_next

instead of:

        lis r2, 0
        ori r2, r2, 32768
        cmpw cr0, r3, r2
        bne cr0, LBB1_2 ;cond_next


2. Codegen this comparison:
      if (X == 0x12345678)

as:

        xoris r2, r3, 4660
        cmplwi cr0, r2, 22136
        bne cr0, LBB1_2 ;cond_next

instead of:

        lis r2, 4660
        ori r2, r2, 22136
        cmpw cr0, r3, r2
        bne cr0, LBB1_2 ;cond_next


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30509 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 04:25:47 +00:00
Chris Lattner
cc96ac3a7d Add a note that we should match rlwnm better 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30508 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 03:59:25 +00:00
Chris Lattner
3fe6c1d389 Legalize is no longer limited to cleverness with just constant shift amounts. 
Allow it to be clever when possible and fall back to the gross code when needed.

This allows us to compile:

long long foo1(long long X, int C) {
  return X << (C|32);
}
long long foo2(long long X, int C) {
  return X << (C&~32);
}

to:
_foo1:
        rlwinm r2, r5, 0, 27, 31
        slw r3, r4, r2
        li r4, 0
        blr


        .globl  _foo2
        .align  4
_foo2:
        rlwinm r2, r5, 0, 27, 25
        subfic r5, r2, 32
        slw r3, r3, r2
        srw r5, r4, r5
        or r3, r3, r5
        slw r4, r4, r2
        blr

instead of:

_foo1:
        ori r2, r5, 32
        subfic r5, r2, 32
        addi r6, r2, -32
        srw r5, r4, r5
        slw r3, r3, r2
        slw r6, r4, r6
        or r3, r3, r5
        slw r4, r4, r2
        or r3, r3, r6
        blr


        .globl  _foo2
        .align  4
_foo2:
        rlwinm r2, r5, 0, 27, 25
        subfic r5, r2, 32
        addi r6, r2, -32
        srw r5, r4, r5
        slw r3, r3, r2
        slw r6, r4, r6
        or r3, r3, r5
        slw r4, r4, r2
        or r3, r3, r6
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30507 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-20 03:47:40 +00:00
Rafael Espindola
4d4c021758 fix header 
add comments
untabify


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30486 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-19 16:41:40 +00:00
Rafael Espindola
71f3b94fa8 Implement a MachineFunctionPass to fix the mul instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30485 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-19 15:49:25 +00:00
Chris Lattner
f529b08c0d item done 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30483 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-19 06:19:03 +00:00
Chris Lattner
cf9d0acfef Fold the PPCISD shifts when presented with 0 inputs. This occurs for code 
like:
long long test(long long X, int Y) {
  return 1ULL << Y;
}
long long test2(long long X, int Y) {
  return -1LL << Y;
}

which we used to compile to:

_test:
        li r2, 1
        subfic r3, r5, 32
        li r4, 0
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r4, r5
        slw r6, r2, r6
        or r3, r4, r3
        slw r4, r2, r5
        or r3, r3, r6
        blr
_test2:
        li r2, -1
        subfic r3, r5, 32
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r2, r5
        slw r2, r2, r6
        or r3, r4, r3
        or r3, r3, r2
        blr

Now we produce:

_test:
        li r2, 1
        addi r3, r5, -32
        subfic r4, r5, 32
        slw r3, r2, r3
        srw r4, r2, r4
        or r3, r4, r3
        slw r4, r2, r5
        blr
_test2:
        li r2, -1
        subfic r3, r5, 32
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r2, r5
        slw r2, r2, r6
        or r3, r4, r3
        or r3, r3, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30479 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-19 05:22:59 +00:00
Andrew Lenharth
2ab804c607 A pass to remove the worst of the replay trap offenders, and as a bonus, align basic blocks when it is free to do so 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30467 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-18 19:44:29 +00:00
Andrew Lenharth
ea4f9d5801 Jump tables on Alpha 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30463 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-18 18:01:03 +00:00
Chris Lattner
f73fb88688 add a note. Our 64-bit shifts are ~30% slower than gcc's 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30457 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-18 05:36:54 +00:00
Chris Lattner
b33a42a21f This is closer to what we really want. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30451 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-18 04:54:35 +00:00
Anton Korobeynikov
bcb9770efe Added some eye-candy for Subtarget type checking 
Added X86 StdCall & FastCall calling conventions. Codegen will follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30446 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-17 20:25:45 +00:00
Anton Korobeynikov
93c2b37340 Small fixes for supporting dll* linkage types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30441 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-17 13:06:18 +00:00
Chris Lattner
7ed96abc09 add a note noticed through source inspection 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30418 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-16 23:57:51 +00:00
Chris Lattner
88640b5ecd add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30406 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-16 03:30:19 +00:00
Chris Lattner
cbce2f6c1b add a nate note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30399 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-15 20:31:36 +00:00
Evan Cheng
c45a2c72cc Remove a unnecessary check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30382 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-14 23:55:02 +00:00
Chris Lattner
f0613e1e7c add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30377 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-14 20:56:30 +00:00
Anton Korobeynikov
b74ed07bfd Adding dllimport, dllexport and external weak linkage types. 
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30374 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-14 18:23:27 +00:00
Chris Lattner
08c33011d1 add note about switch lowering 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30308 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 23:37:16 +00:00
Evan Cheng
80543c8305 Skip over first operand when determining REX prefix for two-address code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30300 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 19:07:28 +00:00
Chris Lattner
bfd68a7858 Turn X < 0 -> TEST X,X js 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30294 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 17:04:54 +00:00
Chris Lattner
7a6366de86 The sense of this branch was inverted :( 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30293 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 16:56:12 +00:00
Rafael Espindola
3ad5e5cf99 add shifts to addressing mode 1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 12:09:43 +00:00
Chris Lattner
0f27fc34f7 Fix a regression in the 32-bit port from the 64-bit port landing. 
We now compile CodeGen/X86/lea-2.ll into:

_test:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        leal -5(%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl 4(%esp), %eax
        leal (,%eax,4), %eax
        addl 8(%esp), %eax
        addl $4294967291, %eax
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30288 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 04:45:25 +00:00
Chris Lattner
d1468d3332 new note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30286 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 04:19:50 +00:00
Chris Lattner
95af34e33f new note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30285 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 03:54:54 +00:00
Chris Lattner
f95705163f Compile X > -1 -> text X,X; js dest 
This implements CodeGen/X86/jump_sign.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30283 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-13 03:22:10 +00:00
Evan Cheng
c356a572e3 Reflects MachineConstantPoolEntry changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30279 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-12 21:04:05 +00:00
Chris Lattner
adaa38f13d add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30271 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-12 06:36:01 +00:00
Chris Lattner
0bfd7fde43 Testcase noticed from PR906 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30269 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 23:00:56 +00:00
Chris Lattner
2a33a3f08d add compilable testcase 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30268 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 22:57:51 +00:00
Rafael Espindola
817e7fdb8b implement SRL and MUL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30262 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 19:24:19 +00:00
Rafael Espindola
1b3956b516 add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30261 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 19:23:32 +00:00
Rafael Espindola
7cca7c5317 partial implementation of the ARM Addressing Mode 1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30252 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 17:25:40 +00:00
Rafael Espindola
ff59d22232 call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30246 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 12:49:38 +00:00
Evan Cheng
f47d167c3b Updates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30245 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-11 05:35:17 +00:00