836 Commits

Author SHA1 Message Date
Sanjay Patel
70a10441b9 [TargetLowering] add tests to show effect of setcc sub->shift; NFC
There's effectively no difference for the cases with variables.
We just trade a sub for an add on those. But the case with a
subtract from constant would require an extra move instruction
on x86, so this looks like a reasonable generic combine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353619 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-09 17:03:59 +00:00
Sanjay Patel
af9730abe5 [TargetLowering] avoid miscompile in setcc transform (PR40657)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353615 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-09 15:59:02 +00:00
Nikita Popov
b58596f863 Revert "[SelectionDAG] Extract [US]MULO expansion into TL method; NFC"
This reverts commit r353611.

Triggers an assertion during the libcall expansion on ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353612 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-09 13:54:02 +00:00
Nikita Popov
fe7822a4a2 [SelectionDAG] Extract [US]MULO expansion into TL method; NFC
In preparation for supporting vector expansion.

Also drop a variant of ExpandLibCall, of which the MULO expansions
were the only user.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353611 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-09 13:29:22 +00:00
Craig Topper
e3696113b6 Implementation of asm-goto support in LLVM
This patch accompanies the RFC posted here:
http://lists.llvm.org/pipermail/llvm-dev/2018-October/127239.html

This patch adds a new CallBr IR instruction to support asm-goto
inline assembly like gcc as used by the linux kernel. This
instruction is both a call instruction and a terminator
instruction with multiple successors. Only inline assembly
usage is supported today.

This also adds a new INLINEASM_BR opcode to SelectionDAG and
MachineIR to represent an INLINEASM block that is also
considered a terminator instruction.

There will likely be more bug fixes and optimizations to follow
this, but we felt it had reached a point where we would like to
switch to an incremental development model.

Patch by Craig Topper, Alexander Ivchenko, Mikhail Dvoretckii

Differential Revision: https://reviews.llvm.org/D53765

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353563 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-08 20:48:56 +00:00
Simon Pilgrim
d5cf0c957e [TargetLowering] Use ISD::FSHR in expandFixedPointMul
Replace OR(SHL,SRL) pattern with ISD::FSHR (legalization expands this later if necessary) - this helps with the scale == 0 'undefined' drop-through case that was discussed on D55720.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353546 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-08 18:57:38 +00:00
Simon Pilgrim
de0c5e9f25 [TargetLowering] Add SimplifyDemandedBits funnel shift support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353539 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-08 17:19:01 +00:00
Nirav Dave
ae502dc0ce [InlineAsm][X86] Add backend support for X86 flag output parameters.
Allow custom handling of inline assembly output parameters and add X86
flag parameter support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353307 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-06 15:26:29 +00:00
Leonard Chan
18c82e623e [Intrinsic] Unsigned Fixed Point Multiplication Intrinsic
Add an intrinsic that takes 2 unsigned integers with the scale of them
provided as the third argument and performs fixed point multiplication on
them.

This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.

Differential Revision: https://reviews.llvm.org/D55625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353059 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-04 17:18:11 +00:00
Sanjay Patel
e9dc79169d [TargetLowering] try harder to determine undef elements of vector binops
This might be the start of tracking all vector element constants generally if we take it to its 
logical conclusion, but let's stop here and make sure this is correct/beneficial so far.

The affected tests require a convoluted path before they get simplified currently because we 
don't call SimplifyDemandedVectorElts() from binops directly and don't modify the binop operands 
directly in SimplifyDemandedVectorElts().

That's why the tests all have a trailing shuffle to induce a chain reaction of transforms. So 
something like this is happening:

1. Improve the knowledge of undefs in the binop via a SimplifyDemandedVectorElts() call that 
   originates from a shuffle.
2. Transfer that undef knowledge back to the shuffle mask user as more undef lanes.
3. Combine the modified shuffle by calling SimplifyDemandedVectorElts() again.
4. Translate the improved shuffle mask as undemanded lanes of build vector constants causing 
   those to become full undef constants.
5. Simplify the binop now that it has a full undef operand.

As we can see from the unchanged 'and' and 'or' tests, tracking undefs alone isn't a full solution. 
We would need to track zero and all-ones constants to improve those opcodes. We'd probably need to 
track NaN for FP ops too (assuming we don't have fast-math-flags set).

Differential Revision: https://reviews.llvm.org/D57066


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352880 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-01 15:35:12 +00:00
Leonard Chan
d68d001a2c [Intrinsic] Expand SMULFIX to MUL, MULH[US], or [US]MUL_LOHI on vector arguments
r zero scale SMULFIX, expand into MUL which produces better code for X86.

For vector arguments, expand into MUL if SMULFIX is provided with a zero scale.
Otherwise, expand into MULH[US] or [US]MUL_LOHI.

Differential Revision: https://reviews.llvm.org/D56987

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352783 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-31 19:15:37 +00:00
James Y Knight
b21d80e08f Adjust documentation for git migration.
This fixes most references to the paths:
 llvm.org/svn/
 llvm.org/git/
 llvm.org/viewvc/
 github.com/llvm-mirror/
 github.com/llvm-project/
 reviews.llvm.org/diffusion/

to instead point to https://github.com/llvm/llvm-project.

This is *not* a trivial substitution, because additionally, all the
checkout instructions had to be migrated to instruct users on how to
use the monorepo layout, setting LLVM_ENABLE_PROJECTS instead of
checking out various projects into various subdirectories.

I've attempted to not change any scripts here, only documentation. The
scripts will have to be addressed separately.

Additionally, I've deleted one document which appeared to be outdated
and unneeded:
  lldb/docs/building-with-debug-llvm.txt

Differential Revision: https://reviews.llvm.org/D57330

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352514 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-29 16:37:27 +00:00
Nikita Popov
98d9d8b1f1 [CodeGen][X86] Expand UADDSAT to NOT+UMIN+ADD
Followup to D56636, this time handling the UADDSAT case by expanding
uadd.sat(a, b) to umin(a, ~b) + b.

Differential Revision: https://reviews.llvm.org/D56869

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352409 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-28 19:19:09 +00:00
Simon Pilgrim
827ebc9db7 [TargetLowering] Rename getExpandedFixedPointMultiplication to expandFixedPointMul. NFCI.
Match the (much shorter) name used in various legalization methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352056 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-24 15:46:54 +00:00
Chandler Carruth
6b547686c5 Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351636 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-19 08:50:56 +00:00
Nikita Popov
b96b37dc8f Reapply "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors"
Related to https://bugs.llvm.org/show_bug.cgi?id=40123.

Rather than scalarizing, expand a vector USUBSAT into UMAX+SUB,
which produces much better code for X86.

Reapplying with updated SLPVectorizer tests.

Differential Revision: https://reviews.llvm.org/D56636

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351219 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-15 18:43:41 +00:00
Nikita Popov
f0a0953bb6 Revert "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors"
This reverts commit r351125.

I missed test changes in an SLPVectorizer test, due to the cost model
changes. Reverting for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351129 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-14 22:18:39 +00:00
Nikita Popov
ec124e9d4d [CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors
Related to https://bugs.llvm.org/show_bug.cgi?id=40123.

Rather than scalarizing, expand a vector USUBSAT into UMAX+SUB,
which produces much better code for X86.

Differential Revision: https://reviews.llvm.org/D56636

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351125 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-14 21:43:30 +00:00
Nikita Popov
b1e7adfcfe [X86] Rename overly verbose method; NFC
As suggested on D56636.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351021 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-13 16:41:26 +00:00
Simon Pilgrim
019755c53e Use getShiftAmountTy for shift amounts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351005 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-12 12:00:43 +00:00
Simon Pilgrim
927c2b0273 [X86][AARCH64] Improve ISD::ABS support
This patch takes some of the code from D49837 to allow us to enable ISD::ABS support for all SSE vector types.

Differential Revision: https://reviews.llvm.org/D56544

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350998 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-12 09:59:32 +00:00
Stanislav Mekhanoshin
26652ec519 Remove check for single use in ShrinkDemandedConstant
This removes check for single use from general ShrinkDemandedConstant
to the BE because of the AArch64 regression after D56289/rL350475.

After several hours of experiments I did not come up with a testcase
failing on any other targets if check is not performed.

Moreover, direct call to ShrinkDemandedConstant is not really needed
and superceed by SimplifyDemandedBits.

Differential Revision: https://reviews.llvm.org/D56406

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350684 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-09 02:24:22 +00:00
Craig Topper
2d88ada4d7 [TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes a User and OpIdx. Stop using it in AMDGPU target for simplifyI24.
As we saw in D56057 when we tried to use this function on X86, it's unsafe. It allows the operand node to have multiple users, but doesn't prevent recursing past the first node when it does have multiple users. This can cause other simplifications earlier in the graph without regard to what bits are needed by the other users of the first node. Ideally all we should do to the first node if it has multiple uses is bypass it when its not needed by the user we started from. Doing any other transformation that SimplifyDemandedBits can do like turning ZEXT/SEXT into AEXT would result in an increase in instructions.

Fortunately, we already have a function that can do just that, GetDemandedBits. It will only make transformations that involve bypassing a node.

This patch changes AMDGPU's simplifyI24, to use a combination of GetDemandedBits to handle the multiple use simplifications. And then uses the regular SimplifyDemandedBits on each operand to handle simplifications allowed when the operand only has a single use. Unfortunately, GetDemandedBits simplifies constants more aggressively than SimplifyDemandedBits. This caused the -7 constant in the changed test to be simplified to remove the upper bits. I had to modify computeKnownBits to account for this by ignoring the upper 8 bits of the input.

Differential Revision: https://reviews.llvm.org/D56087

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350560 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-07 19:30:43 +00:00
Stanislav Mekhanoshin
f04e8d9380 Added single use check to ShrinkDemandedConstant
Fixes cvt_f32_ubyte combine. performCvtF32UByteNCombine() could shrink
source node to demanded bits only even if there are other uses.

Differential Revision: https://reviews.llvm.org/D56289

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350475 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-05 19:20:00 +00:00
Simon Pilgrim
ad5be70b1a [SelectionDAG] Always use the version of computeKnownBits that returns a value. NFCI.
Continues the work started by @bogner in rL340594 to remove uses of the KnownBits output paramater version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349907 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-21 14:56:18 +00:00
Simon Pilgrim
cd3782549e [TargetLowering] Fix propagation of undefs in zero extension ops (PR40091)
As described on PR40091, we have several places where zext (and zext_vector_inreg) fold an undef input into an undef output. For zero extensions this is incorrect as the output should guarantee to least have the new upper bits set to zero.

SimplifyDemandedVectorElts is the worst offender (and its the most likely to cause new undefs to appear) but DAGCombiner's tryToFoldExtendOfConstant has a similar issue.

Thanks to @dmgreen for catching this.

Differential Revision: https://reviews.llvm.org/D55883

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349625 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-19 13:37:59 +00:00
Simon Pilgrim
fe8acf3ad3 [TargetLowering] Fallback from SimplifyDemandedVectorElts to SimplifyDemandedBits
For opcodes not covered by SimplifyDemandedVectorElts, SimplifyDemandedBits might be able to help now that it supports demanded elts as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349466 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-18 09:33:25 +00:00
JF Bastien
1ea2e05be9 NFC: remove unused variable
D55768 removed its use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349377 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-17 19:03:24 +00:00
Simon Pilgrim
1987714929 [TargetLowering] Add DemandedElts mask to SimplifyDemandedBits (PR40000)
This is an initial patch to add the necessary support for a DemandedElts argument to SimplifyDemandedBits, more closely matching computeKnownBits and to help improve vector codegen.

I've added only a small amount of the changes necessary to get at least one test to update - a lot more can be done but I'd like to add these methodically with proper test coverage, at the same time the hope is to slowly move some/all of SimplifyDemandedVectorElts into SimplifyDemandedBits as well.

Differential Revision: https://reviews.llvm.org/D55768

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349374 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-17 18:43:43 +00:00
Simon Pilgrim
1fe1ffe00e [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorElts
Differential Revision: https://reviews.llvm.org/D55600

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349264 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-15 11:36:36 +00:00
Simon Pilgrim
8ab90583ee [TargetLowering] Add ISD::ROTL/ROTR vector expansion
Move existing rotation expansion code into TargetLowering and set it up for vectors as well.

Ideally this would share more of the funnel shift expansion, but we handle the shift amount modulo quite differently at the moment.

Begun removing x86 vector rotate custom lowering to use the expansion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349025 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-13 11:20:48 +00:00
Simon Pilgrim
2253059902 [TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorElts
If either of the operand elements are zero then we know the result element is going to be zero (even if the other element is undef).

Differential Revision: https://reviews.llvm.org/D55558

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348926 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-12 13:43:07 +00:00
Leonard Chan
8e3fdeb3b8 [Intrinsic] Signed Fixed Point Multiplication Intrinsic
Add an intrinsic that takes 2 signed integers with the scale of them provided
as the third argument and performs fixed point multiplication on them.

This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.

Differential Revision: https://reviews.llvm.org/D54719

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348912 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-12 06:29:14 +00:00
Simon Pilgrim
4653c9ad51 [TargetLowering] Add ISD::EXTRACT_VECTOR_ELT support to SimplifyDemandedBits
Let SimplifyDemandedBits attempt to simplify all elements of a vector extraction.

Part of PR39689.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348839 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-11 11:08:40 +00:00
Simon Pilgrim
db716b5543 [TargetLowering] Add UNDEF folding to SimplifyDemandedVectorElts
If all the demanded elements of the SimplifyDemandedVectorElts are known to be UNDEF, we can simplify to an ISD::UNDEF node.

Zero constant folding will be handled in a future patch - its a little trickier as we often have bitcasted zero values.

Differential Revision: https://reviews.llvm.org/D55511

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348784 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-10 18:29:46 +00:00
Simon Pilgrim
b2a7ed6a26 [TargetLowering] Remove ISD::ANY_EXTEND/ANY_EXTEND_VECTOR_INREG opcodes from SimplifyDemandedVectorElts
These have no test coverage and the KnownZero flags can't be guaranteed unlike SIGN/ZERO_EXTEND cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348361 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-05 12:20:05 +00:00
Simon Pilgrim
67f4757dce [SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)
This is an initial patch to add a minimum level of support for funnel shifts to the SelectionDAG and to begin wiring it up to the X86 SHLD/SHRD instructions.

Some partial legalization code has been added to handle the case for 'SlowSHLD' where we want to expand instead and I've added a few DAG combines so we don't get regressions from the existing DAG builder expansion code.

Differential Revision: https://reviews.llvm.org/D54698

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348353 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-05 11:12:12 +00:00
Simon Pilgrim
cf6cfbd9bb [TargetLowering] SimplifyDemandedVectorElts - don't alter DemandedElts mask
Fix potential issue with the ISD::INSERT_VECTOR_ELT case tweaking the DemandedElts mask instead of using a local copy - so later uses of the mask use the tweaked version.....

Noticed while investigating adding zero/undef folding to SimplifyDemandedVectorElts and the altered DemandedElts mask was causing mismatches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348348 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-05 10:37:45 +00:00
Nirav Dave
02f12eea5e [SelectionDAG] Redefine isGAPlusOffset in terms of unwrapAddress. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348288 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-04 17:59:43 +00:00
Simon Pilgrim
2f5801a565 [TargetLowering] expandFP_TO_UINT - avoid FPE due to out of range conversion (PR17686)
PR17686 demonstrates that for some targets FP exceptions can fire in cases where the FP_TO_UINT is expanded using a FP_TO_SINT instruction.

The existing code converts both the inrange and outofrange cases using FP_TO_SINT and then selects the result, this patch changes this for 'strict' cases to pre-select the FP_TO_SINT input and the offset adjustment.

The X87 cases don't need the strict flag but generates much nicer code with it....

Differential Revision: https://reviews.llvm.org/D53794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348251 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-04 11:21:30 +00:00
Simon Pilgrim
8254306a0e [TargetLowering] Add SimplifyDemandedVectorElts support to EXTEND opcodes
Add support for ISD::*_EXTEND and ISD::*_EXTEND_VECTOR_INREG opcodes.

The extra broadcast in trunc-subvector.ll will be fixed in an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348246 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-04 10:41:06 +00:00
Simon Pilgrim
b0510431f2 [SelectionDAG] Improve SimplifyDemandedBits to SimplifyDemandedVectorElts simplification
D52935 introduced the ability for SimplifyDemandedBits to call SimplifyDemandedVectorElts through BITCASTs if the demanded bit mask entirely covered the sub element.

This patch relaxes this to demanding an element if we need any bit from it.

Differential Revision: https://reviews.llvm.org/D54761

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348073 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-01 12:08:55 +00:00
Simon Pilgrim
d0658beb2f [TargetLowering] SimplifyDemandedBits - only reduce known bits for integer constants
Avoids fuzzing crash found by Mikael Holmén.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347393 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-21 14:26:19 +00:00
Simon Pilgrim
f1f291e60c [DAGCombine] Add calls to SimplifyDemandedVectorElts from visitINSERT_SUBVECTOR (PR37989)
This uncovered an off-by-one typo in SimplifyDemandedVectorElts's INSERT_SUBVECTOR handling as its bounds check was bailing on safe indices.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347313 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-20 15:23:50 +00:00
Simon Pilgrim
8f862e5873 [TargetLowering] Improve SimplifyDemandedVectorElts/SimplifyDemandedBits support
For bitcast nodes from larger element types, add the ability for SimplifyDemandedVectorElts to call SimplifyDemandedBits by merging the elts mask to a bits mask.

I've raised https://bugs.llvm.org/show_bug.cgi?id=39689 to deal with the few places where SimplifyDemandedBits's lack of vector handling is a problem.

Differential Revision: https://reviews.llvm.org/D54679

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347301 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-20 12:02:16 +00:00
Simon Pilgrim
ab88d0c40f [TargetLowering] expandFP_TO_UINT - improve fp16 support
As discussed on D53794, for float types with ranges smaller than the destination integer type, then we should be able to just use a regular FP_TO_SINT opcode.

I thought we'd need to provide MSA test cases for very small integer types as well (fp16 -> i8 etc.), but it turns out that promotion will kick in so they're unnecessary.

Differential Revision: https://reviews.llvm.org/D54703

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347251 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-19 19:16:13 +00:00
Simon Pilgrim
0478924a37 [TargetLowering] Cleanup more of the EXTEND demanded bits cases so that they match. NFCI.
Use the same variable names etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347045 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-16 12:26:26 +00:00
Simon Pilgrim
e3b515280e [TargetLowering] Begin generalizing TargetLowering::expandFP_TO_SINT support. NFCI.
Prior to initial work to add vector expansion support, remove assumptions that we're working on scalar types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346139 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-05 15:49:09 +00:00
Simon Pilgrim
03e8599949 [LegalizeDAG] Add generic vector CTPOP expansion (PR32655)
This patch adds support for expanding vector CTPOP instructions and removes the x86 'bitmath' lowering which replicates the same expansion.

Differential Revision: https://reviews.llvm.org/D53258

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345869 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-01 18:22:11 +00:00
Stanislav Mekhanoshin
832efd7ec3 Check shouldReduceLoadWidth from SimplifySetCC
SimplifySetCC could shrink a load without checking for
profitability or legality of such shink with a target.

Added checks to prevent shrinking of aligned scalar loads
in AMDGPU below dword as scalar engine does not support it.

Differential Revision: https://reviews.llvm.org/D53846

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345778 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 21:24:30 +00:00