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1977 Commits

Author SHA1 Message Date
Dan Gohman
f595141525 Revert 107840 107839 107813 107804 107800 107797 107791. 
Debug info intrinsics win for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-08 01:00:56 +00:00
Chris Lattner
9fc05227a2 Implement the major chunk of PR7195: support for 'callw' 
in the integrated assembler.  Still some discussion to be
done.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 22:27:31 +00:00
Dan Gohman
eabaed26c3 Give FunctionLoweringInfo an MBB member, avoiding the need to pass it 
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 16:47:08 +00:00
Jakob Stoklund Olesen
a4e1ba53dd Add a new target independent COPY instruction and code to lower it. 
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.

COPY is lowered to native register copies by LowerSubregs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 22:29:50 +00:00
Jakob Stoklund Olesen
65766ce7df Clean up TargetOpcodes.h a bit, and limit the number of places where the full 
list of predefined instructions appear. Add some consistency checks.

Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-02 21:44:22 +00:00
Duncan Sands
ef36d864d6 Remove unused variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106834 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-25 09:35:33 +00:00
Bob Wilson
e9c2615b76 Change array references to match my previous change to use the public type 
names for the array fields.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106803 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:21:19 +00:00
Bob Wilson
1ac27cf5ae Fix up some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106795 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:04:30 +00:00
Bob Wilson
9969bc3d19 Use the struct tags mandated by ARM's ABI. Also use the public type names for 
the array fields in these structs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-24 22:03:41 +00:00
Nico Weber
50b9efc2a8 Add support for the x86 instructions "pusha" and "popa". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 20:00:58 +00:00
Bruno Cardoso Lopes
81cd7ffe45 Fix a tblgen bug. 
Given the pattern below as an example:
list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1,
                            (mem_frag addr:$src2))))];

The right reference resolving should lead to:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1,
                            (mem_frag addr:$src2))))];
But was yielding:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1,
                            (mem_frag addr:$src2))))];

Fix this by passing the right name when creating a new DagInit node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106670 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 19:50:39 +00:00
Nick Lewycky
ec4c02d252 Don't link against libm and libpthread which don't exist in BeOS/Haiku. Also, 
Haiku like Linux provides <regex.h>, so use it. Patch by Paul Davey!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106620 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-23 06:48:34 +00:00
Bruno Cardoso Lopes
e5104ac99a Fix a subtle multiclass bug: when using class inheritance on 
a toplevel 'defm', make sure to properly resolve references.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 20:30:50 +00:00
Eric Christopher
1f4a1493fb Remove isTwoAddress from llvm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106470 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 20:35:09 +00:00
Nate Begeman
c4a1b652b2 Add support for returning multiple vectors via sret, which is how the ARM target expects the intrinsics to work. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106406 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-20 21:09:52 +00:00
Dale Johannesen
10416803c1 An attempt to fix the problem Anton reported with 
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 20:44:28 +00:00
Bruno Cardoso Lopes
6e0a99a7ab Teach tablegen how to inherit from classes in 'defm' definitions. 
The rule is simple: only inherit from a class list if they come
in the end, after the last multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106305 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 19:53:41 +00:00
Dan Gohman
a606d955de Start TargetRegisterClass indices at 0 instead of 1, so that 
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-18 18:13:55 +00:00
Bruno Cardoso Lopes
93583c97f8 In case Rec is a definition and not a class, do the proper comparison! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106246 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 23:00:16 +00:00
Nate Begeman
f8c4c27d84 Modify tablegen to support generating all NEON code used by clang at once. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106207 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 04:15:13 +00:00
Bruno Cardoso Lopes
477bf62048 Fix the handling of !if result, avoiding null results for non 'int'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 01:50:39 +00:00
Bruno Cardoso Lopes
eba8f1893b For a tablegen expression such as !if(a,b,c), let 'a' 
be evaluated for 'bit' operators


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 00:31:36 +00:00
Sean Hunt
e3f647360c Fix the typo in my previous one-line commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-17 00:10:16 +00:00
Sean Hunt
a85e1957dd Make sure CMake can build the files added by my previous commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106178 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 23:52:37 +00:00
Sean Hunt
16171446c6 Add preliminary clang attribute generation support. 
The attribute class generation support is still somewhat limited.
See the accompanying clang commit for more details.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106174 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 23:45:50 +00:00
Bruno Cardoso Lopes
e87de41189 let the '!eq' expression support 'int' and 'bit' types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106171 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-16 23:24:12 +00:00
Nate Begeman
4da883a56f Make VC++ happy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106054 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 22:10:31 +00:00
Dale Johannesen
6470a116f1 Next round of tail call changes. Register used in a tail 
call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 22:08:33 +00:00
Chris Lattner
f6c4a30984 generate better code in CheckComplexPattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105970 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 22:33:34 +00:00
Nate Begeman
918f8e4ab0 Add the last of the SemaChecking-gen code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-14 05:17:23 +00:00
Nate Begeman
d72c900152 Add a helping of comments 
Add code for generating bits of semachecking


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105907 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-13 04:47:03 +00:00
Chris Lattner
5ca96988b0 declare a class with 'class' instead of struct to avoid tag mismatch 
warnings, and don't shift by a bool.  Patch by Rizky Herucakra!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105886 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 15:46:56 +00:00
Nate Begeman
cc3c41a9c3 Add generic vector support for bitselect & element byteswap 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105874 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-12 03:09:49 +00:00
Bruno Cardoso Lopes
c902a59f4c More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm) 
Introduce the VEX_X field


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-11 23:50:47 +00:00
Bob Wilson
1a913ed178 Add instruction encoding for the Neon VMOV immediate instruction. This changes 
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction.  This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed.  Testcase for the encoding will follow later when MC has
more support for ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-11 21:34:50 +00:00
Nate Begeman
d6645dd4fe Add support for polynomial type, for polynomial multiply 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-10 18:06:07 +00:00
Bruno Cardoso Lopes
ee65db3add Teach tablegen to allow "let" expressions inside multiclasses, 
providing more ways to factor out commonality from the records.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105776 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-10 02:42:59 +00:00
Nate Begeman
4b425a8caa NEON support for _lane ops, and multiplies by scalar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-10 00:16:56 +00:00
Nate Begeman
f50551eb08 Further refine types for operations which take scalars. 
This will be used primarily by NEON shift intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105733 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 18:02:26 +00:00
Eric Christopher
622dffde86 How about ULL... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105726 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 16:16:48 +00:00
Nate Begeman
007afe4b4b Specialize I-Class instructions better so that we have less work to do in codegen. 
Parenthesize macro args


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105682 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 05:11:55 +00:00
Nate Begeman
6c060dbf84 Handle instructions which need to be #defines for the purpose of capturing constant arguments 
Handle extract hi/lo with common code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105666 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 01:09:00 +00:00
Bruno Cardoso Lopes
99405df044 Reapply r105521, this time appending "LLU" to 64 bit 
immediates to avoid breaking the build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 22:51:23 +00:00
Nate Begeman
96ec22d683 Fix a valgrind error. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105600 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 07:11:17 +00:00
Nate Begeman
5638783276 Refine BuiltinsARM.def types a bit, we should do a better job of this to save some c++ code in CGBuiltins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105598 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 06:01:16 +00:00
Nate Begeman
900f4674c1 ARM NEON: 
fix vcvt naming
handle vdup, vcombine with generic vector code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 00:14:42 +00:00
Nate Begeman
b0a4e4554e clang codegen support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-07 16:00:37 +00:00
Chris Lattner
1087f54ddb revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
3eca98bb3a Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-05 03:53:24 +00:00
Bruno Cardoso Lopes
270562b3d4 Teach tablegen to support 'defm' inside multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105519 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-05 02:11:52 +00:00
Nate Begeman
9e584b37b0 Handle multi-vector returns and args. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105496 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 22:53:30 +00:00
Nate Begeman
7c21f747c7 Additional fixes to BuiltinsARM.def generator, on to clang codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 21:36:00 +00:00
Nate Begeman
92f98af9fb Progress on generating BuiltinsARM.def, still some duplicates to work out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105461 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 07:11:25 +00:00
Nate Begeman
73cef3e9b1 BuiltinsARM.def emitter, still needs a substantial bit of tweaking to lighten the load on clang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105456 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 01:26:15 +00:00
Nate Begeman
a8979a0e7b Mangle __builtin_neon_* names appropriately. 
Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105443 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 00:21:41 +00:00
Nate Begeman
3861e74490 Add some additional capabilities to the neon emitter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105416 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 21:35:22 +00:00
Dale Johannesen
51e28e6348 Early implementation of tail call for ARM. 
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 21:09:53 +00:00
Nate Begeman
162d3ba464 arm_neon.h now makes it through clang and generates appropriate code for those functions which can use 
generic vector operators rather than __builtin_neon_*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 04:04:09 +00:00
Nate Begeman
7c8c8830a9 arm_neon.h emitter now mostly complete for the purposes of initial testing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105349 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 21:53:00 +00:00
Duncan Sands
8dbbacedcd Pacify recent gcc: remove a pointless const qualifier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 08:37:30 +00:00
Nate Begeman
e66aab553c Checkpoint; handle 'int' and 'void' correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105316 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 07:14:28 +00:00
Nate Begeman
af905efc61 Emit full function prototypes. Definitions & typedefs to come. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105315 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 06:17:19 +00:00
Nate Begeman
22237771d8 Checkpoint arm_neon.h generation with tablegen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 00:34:55 +00:00
Sean Hunt
891f27380c Fix comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105297 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-01 23:29:39 +00:00
Sean Hunt
c10a62b0d5 Allow for creation of clang DeclNodes tables. 
The StmtNodes generator has been generalized to allow for the
creation of DeclNodes tables as well, and another emitter was
added for DeclContexts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-30 07:21:42 +00:00
Jakob Stoklund Olesen
7c9a6e3284 Emit TargetRegisterInfo::composeSubRegIndices(). 
Also verify that all subregister indices compose unambiguously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 23:48:31 +00:00
Nate Begeman
e8f0349439 Comment out some code in prep for actual .td file checkpoint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104927 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 02:19:08 +00:00
Eli Friedman
a4fda2c757 Fix build breakage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104912 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 01:15:28 +00:00
Nate Begeman
5ddb087f7f Add support to tablegen for auto-generating arm_neon.h from a tablegen description 
of the intrinsics.  The goal is to auto-generate both support for GCC-style (vector)
and ARM-style (struct of vector) intrinsics.

This is work in progress, but will be completed soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104910 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 01:08:32 +00:00
Dan Gohman
9d2cbffed0 Simplify raw_ostream usage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104874 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 19:48:08 +00:00
Dan Gohman
098d3a41e1 Minor code simplification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 16:25:05 +00:00
Daniel Dunbar
368a456503 AsmMatcher: Ensure classes are totally ordered, so we can std::sort them reliably. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 05:31:32 +00:00
Jakob Stoklund Olesen
6f0ff1d578 Check that inherited subregisters all have a direct SubRegIndex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 22:15:07 +00:00
Jakob Stoklund Olesen
160a3bf74d Add StringRef::compare_numeric and use it to sort TableGen register records. 
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 21:47:28 +00:00
Jakob Stoklund Olesen
f86a619314 Suppress emmission of empty subreg/superreg/alias sets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104741 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 21:35:55 +00:00
Jakob Stoklund Olesen
ca561ffcf3 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 17:27:12 +00:00
Jakob Stoklund Olesen
b555609e73 Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
6a45d681e5 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 00:28:19 +00:00
Jakob Stoklund Olesen
76f0ad7bf5 Drop the SuperregHashTable. It is essentially the same as SubregHashTable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 23:43:18 +00:00
Jakob Stoklund Olesen
1fc8e759a7 Print symbolic SubRegIndex names on machine operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
48d0c163fb Ignore NumberHack and give each SubRegIndex instance a unique enum value instead. 
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
33276d95ef Switch SubRegSet to using symbolic SubRegIndices 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 23:03:18 +00:00
Chris Lattner
ec5a0b336a diaggroup categories should take precedence over diag-specific groups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104567 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:55:47 +00:00
Jakob Stoklund Olesen
09bc029865 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 21:46:58 +00:00
Jakob Stoklund Olesen
73ea7bf450 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-24 14:48:12 +00:00
Daniel Dunbar
54ddf3d9c7 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 21:02:29 +00:00
Daniel Dunbar
4072886a69 tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor 
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:20:32 +00:00
Sean Hunt
853197557c Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macro 
Also rename ABSTRACT to ABSTRACT_STMT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104018 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-18 06:22:50 +00:00
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 02:13:41 +00:00
Evan Cheng
dbf67fefea Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 23:55:47 +00:00
Chandler Carruth
93ca7b60bf Update tablegen to generate shorts instead of chars for subgroup arrays. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 07:43:47 +00:00
Dan Gohman
a6cb641f48 Add initial kill flag support to FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 23:54:07 +00:00
Douglas Gregor
7d9663c70b Fixes for Microsoft Visual Studio 2010, from Steven Watanabe! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103457 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 06:17:44 +00:00
Sean Callanan
1a8b789a4b Eliminated the classification of control registers into %ecr_ 
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:59:00 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:33:48 +00:00
Evan Cheng
b63387afc6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 06:36:08 +00:00
Sean Hunt
44ed2c31a5 Fix some stylistic issues with my last commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 05:24:38 +00:00
Shantonu Sen
d1dd5ed0ed Add newline to end of file to avoid warning 
when building llvm with clang


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103084 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 13:56:46 +00:00
Sean Hunt
dc896a4118 Include the right header for toupper 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 04:31:44 +00:00
Sean Hunt
84e2f959b7 Add an emitter to handle the list of clang statement nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103071 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 04:13:08 +00:00