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2 Commits

Author SHA1 Message Date
Andrea Di Biagio
638e97f135 Teach the DAGCombiner how to fold 'vselect' dag nodes according 
to the following two rules:
  1) fold (vselect (build_vector AllOnes), A, B) -> A
  2) fold (vselect (build_vector AllZeros), A, B) -> B



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198777 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 18:33:04 +00:00
Cameron McInally
80955805e4 Suppress '(x < y) ? a : 0 -> (x < y) & a' transform on X86 architectures with dedicated mask registers. 
Patch by Aleksey Bader.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196386 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-04 14:52:33 +00:00