Commit Graph

93 Commits

Author SHA1 Message Date
Dmitry Preobrazhensky
a899c6a814 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Corrected a typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365353 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-08 17:09:09 +00:00
Dmitry Preobrazhensky
f295ff3a3e [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- added description of GFX10;
- added description of operands sccz, vccz, lds_direct, etc;
- minor bugfixing and improvements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365347 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-08 16:50:11 +00:00
Yaxun Liu
95d322b634 [AMDGPU] Added a new metadata for multi grid sync implicit argument
Patch by Christudasan Devadasan.

Differential Revision: https://reviews.llvm.org/D63886


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365217 91177308-0d34-0410-b5e6-96231b3b80d8
2019-07-05 16:05:17 +00:00
Nicolai Haehnle
f1a1a392db AMDGPU/MC: Add .amdgpu_lds directive
Summary:
The directive defines a symbol as an group/local memory (LDS) symbol.
LDS symbols behave similar to common symbols for the purposes of ELF,
using the processor-specific SHN_AMDGPU_LDS as section index.

It is the linker and/or runtime loader's job to "instantiate" LDS symbols
and resolve relocations that reference them.

It is not possible to initialize LDS memory (not even zero-initialize
as for .bss).

We want to be able to link together objects -- starting with relocatable
objects, but possible expanding to shared objects in the future -- that
access LDS memory in a flexible way.

LDS memory is in an address space that is entirely separate from the
address space that contains the program image (code and normal data),
so having program segments for it doesn't really make sense.

Furthermore, we want to be able to compile multiple kernels in a
compilation unit which have disjoint use of LDS memory. In that case,
we may want to place LDS symbols differently for different kernels
to save memory (LDS memory is very limited and physically private to
each kernel invocation), so we can't simply place LDS symbols in a
.lds section.

Hence this solution where LDS symbols always stay undefined.

Change-Id: I08cbc37a7c0c32f53f7b6123aa0afc91dbc1748f

Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61493

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364296 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-25 11:51:35 +00:00
Stanislav Mekhanoshin
50d6e67368 [AMDGPU] gfx10 documentation update. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363332 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-13 22:18:47 +00:00
Matt Arsenault
bd31482f3c AMDGPU: Remove amdgpu-max-work-group-size attribute
This has been deprecated for a long time, and mesa recently switched
to amdgpu-flat-work-group-size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362641 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-05 20:32:32 +00:00
Zachary Turner
90e8e81199 Try to fix Sphinx bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357790 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-05 18:06:42 +00:00
Matt Arsenault
234b3a117e AMDGPU: Remove dx10-clamp from subtarget features
Since this can be set with s_setreg*, it should not be a subtarget
property. Set a default based on the calling convention, and Introduce
a new amdgpu-dx10-clamp attribute to override this if desired.

Also introduce a new amdgpu-ieee attribute to match.

The values need to match to allow inlining. I think it is OK for the
caller's dx10-clamp attribute to override the callee, but there
doesn't appear to be the infrastructure to do this currently without
definining the attribute in the generic Attributes.td.

Eventually the calling convention lowering will need to insert a mode
switch somewhere for these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357302 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-29 19:14:54 +00:00
Scott Linder
6209ea9ff7 [AMDGPU] Add an additional Code Object V3 assembler example
Document the intended use of the `.amdgcn.next_free_{s,v}gpr` in the
context of multiple kernels and functions.

Differential Revision: https://reviews.llvm.org/D59949

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357289 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-29 17:49:51 +00:00
Konstantin Zhuravlyov
142ef796c0 AMDGPU: Make sram-ecc off by default for Vega20
Differential Revision: https://reviews.llvm.org/D59718


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357247 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-29 12:04:18 +00:00
Scott Linder
8c243de4d1 [AMDGPU] Clarify Code Object V2/V3 differences in AMDGPUUsage
Ensure Code Object V2 documentation is complete, but always contains a
warning and a link to the equivalent Code Object V3 documentation.

Explicitly indicate that any note records present in a code object that
are not documented must be considered deprecated and ignored.

Differential Revision: https://reviews.llvm.org/D59782

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357176 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-28 15:08:52 +00:00
Konstantin Zhuravlyov
ba71b832d8 AMDGPU: Add support for cross address space synchronization scopes
Differential Revision: https://reviews.llvm.org/D59517


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356946 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-25 20:50:21 +00:00
Neil Henning
89fc4394cb [AMDGPU] Add an experimental buffer fat pointer address space.
Add an experimental buffer fat pointer address space that is currently
unhandled in the backend. This commit reserves address space 7 as a
non-integral pointer repsenting the 160-bit fat pointer (128-bit buffer
descriptor + 32-bit offset) that is heavily used in graphics workloads
using the AMDGPU backend.

Differential Revision: https://reviews.llvm.org/D58957

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356373 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-18 14:44:28 +00:00
Dmitry Preobrazhensky
06d4d4cd59 [AMDGPU][MC][CODEOBJECT] Added predefined symbols to access GPU minor and stepping numbers
Added the following Code Object v3 symbols:
    .amdgcn.gfx_generation_minor
    .amdgcn.gfx_generation_stepping

Reviewers: artem.tamazov, kzhuravl

Differential Revision: https://reviews.llvm.org/D57826

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353515 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-08 13:51:31 +00:00
Dmitry Preobrazhensky
51120d77df [AMDGPU][MC][DOC] Updated AMD GPU assembler description
Stage 2: added detailed description of operands

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349368 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-17 17:38:11 +00:00
Scott Linder
dff71eafb8 [AMDGPU] Update code object metadata format documentation
* Add amdhsa prefix to names to allow other tools to use the metadata
  without collision.
* Make names consistent.
* Simplify structure.
* Change note record ID.
* Switch from YAML to MsgPack format.
* Document metadata assembler directive.

Patch By: t-tye (Tony Tye)
Differential Revision: https://reviews.llvm.org/D53445



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346992 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-15 20:46:55 +00:00
Konstantin Zhuravlyov
ba9a1e1d78 AMDGPU/Docs: Add product names for Vega20
Differential Revision: https://reviews.llvm.org/D54178


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346354 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-07 20:54:16 +00:00
Konstantin Zhuravlyov
ffb90c4641 AMDGPU/Docs: Fix the processor table
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346263 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-06 20:23:53 +00:00
Konstantin Zhuravlyov
7829a6dfd5 AMDGPU: Add sram-ecc feature
Differential Revision: https://reviews.llvm.org/D53222


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346177 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-05 22:44:19 +00:00
Tim Renouf
7d5e5c2747 [AMDGPU] Defined gfx909 Raven Ridge 2
Differential Revision: https://reviews.llvm.org/D53418

Change-Id: Ie3d054f2e956c2768988c0f4c0ffd29a47294eef

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345120 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-24 08:14:07 +00:00
Chandler Carruth
c0cb45a2cf [docs] Turn of nasm highlighting for a code block.
This appears to produce a warning on the docs build bot. It doesn't
reproduce for me, likely because I have a newer (or more full featured)
pygments install.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338978 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-06 01:19:43 +00:00
Konstantin Zhuravlyov
d6794f0ba7 AMDHSA: Put old assembler docs back
Until we switch to code object v3 by default.
Follow up for https://reviews.llvm.org/D47736.

Differential Revision: https://reviews.llvm.org/D48497


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335378 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-22 19:23:18 +00:00
Scott Linder
43cbf8d92e [AMDGPU] Update assembler for HSA Code Object v3
Update AMDGPU assembler syntax behind the code-object-v3 feature:

* Replace/rename most AMDGPU assembler directives/symbols and document them.
* Provide more diagnostics (e.g. values out of range, missing values, repeated
  values).
* Provide path for backwards compatibility, even with underlying descriptor
  changes.

Differential Revision: https://reviews.llvm.org/D47736



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335281 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-21 19:38:56 +00:00
Konstantin Zhuravlyov
3316883bba AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z
and everything that comes with it from implementation
and v3 header files.

Leave definition in v2 header files for backwards
compatibility.

Differential Revision: https://reviews.llvm.org/D48191


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335267 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-21 18:36:04 +00:00
Tony Tye
978dec7518 [AMDGPU] Document the AMDGPU LLVM attributes
Differential Revision: https://reviews.llvm.org/D48101


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334733 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-14 16:40:10 +00:00
Konstantin Zhuravlyov
299cf5ff6a AMDHSA: Code object v3 updates
- Do not emit following assembler directives:
  - .hsa_code_object_version
  - .hsa_code_object_isa
  - .amd_amdgpu_isa
  - .amd_amdgpu_hsa_metadata
  - .amd_amdgpu_pal_metadata
- Do not emit .note entries
- Cleanup and bring in sync kernel descriptor header file
- Emit kernel descriptor into .rodata with appropriate relocations and
  alignments



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334519 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-12 18:02:46 +00:00
Konstantin Zhuravlyov
840f423383 AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as
it is set by CP

Differential Revision: https://reviews.llvm.org/D47392



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333451 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-29 19:09:13 +00:00
Tony Tye
b994738de7 [AMDGPU] Change llvm.debugtrap to be a debug breakpoint that can resume execution.
No longer require the queue pointer to be passed in in fixed SGPRs.

Differential Revision: https://reviews.llvm.org/D46769


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332485 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 16:19:34 +00:00
Matt Arsenault
ac9b3ef76a AMDGPU: Add Vega12 and Vega20
Changes by
  Matt Arsenault
  Konstantin Zhuravlyov

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331215 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-30 19:08:16 +00:00
Tony Tye
efcdcc2677 [AMDGPU] Add gfx902 product names
Differential Revision: https://reviews.llvm.org/D45609


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330081 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-14 01:58:10 +00:00
Tony Tye
f0a27cc4cc [AMDGPU] Update relocation record description
Document which relocation records are static and dynamic.

Differential Revision: https://reviews.llvm.org/D45587


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329981 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-13 01:01:27 +00:00
Hiroshi Inoue
ef1bc2d3ca [NFC] fix trivial typos in documents and comments
"is is" -> "is", "if if" -> "if", "or or" -> "or"



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329878 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-12 05:53:20 +00:00
Tim Corringham
c5e0b13c3b Add AMDPAL Code Conventions section to AMD docs
Summary:
This is a first version of the AMDPAL code conventions.
Further updates will undoubtably be required to fully
document AMDPAL.

Subscribers: nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D45246

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329188 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-04 13:02:09 +00:00
Tony Tye
d31305af4f [AMDGPU] Define code object identification string used in AMDHSA runtimes.
Differential Revision: https://reviews.llvm.org/D44718


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328669 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-27 21:20:46 +00:00
Tony Tye
9272c8addc [AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU
Add two additional implicit arguments for OpenCL for the AMDGPU target using the AMDHSA runtime to support device enqueue.

Differential Revision: https://reviews.llvm.org/D44697


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328351 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-23 18:58:47 +00:00
Tony Tye
2b4b7fe362 [AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU
- Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target.
- Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS.

Differential Revision: https://reviews.llvm.org/D43736


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328349 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-23 18:45:18 +00:00
Eugene Zelenko
e9a0122a40 [Documentation] Fix markup problem in AMDGPUUsage.rst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328116 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-21 17:09:35 +00:00
Craig Topper
17ab24c8db [TableGen] Pass result of std::unique to vector::erase instead of calculating a size and calling resize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328031 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-20 20:24:10 +00:00
Dmitry Preobrazhensky
1eaf2d7b5a [AMDGPU][MC][DOC] Updated AMD GPU assembler description
See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

Differential Revision: https://reviews.llvm.org/D44020

Reviewers: artem.tamazov, vpykhtin

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327288 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-12 15:55:08 +00:00
Tony Tye
636e2230de [AMDGPU] Update AMDGOUUsage.rst descriptions
- Improve description of XNACK ELF flag.
- Rename all uses of wave to wavefront to be consistent.

Differential Revision: https://reviews.llvm.org/D43983


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326989 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-08 05:46:01 +00:00
Scott Linder
5e4b515c4b [DebugInfo] Support DWARF v5 source code embedding extension
In DWARF v5 the Line Number Program Header is extensible, allowing values with
new content types. In this extension a content type is added,
DW_LNCT_LLVM_source, which contains the embedded source code of the file.

Add new optional attribute for !DIFile IR metadata called source which contains
source text. Use this to output the source to the DWARF line table of code
objects. Analogously extend METADATA_FILE in Bitcode and .file directive in ASM
to support optional source.

Teach llvm-dwarfdump and llvm-objdump about the new values. Update the output
format of llvm-dwarfdump to make room for the new attribute on file_names
entries, and support embedded sources for the -source option in llvm-objdump.

Differential Revision: https://reviews.llvm.org/D42765



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325970 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-23 23:01:06 +00:00
Konstantin Zhuravlyov
16290892d3 AMDGPU: Bring elf flags in sync with the spec
- Add MACH flags
- Add XNACK flag
- Add reserved flags
- Minor cleanups in docs

Differential Revision: https://reviews.llvm.org/D43356


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325399 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-16 22:33:59 +00:00
Yaxun Liu
2930e5c52d [AMDGPU] Change constant addr space to 4
Differential Revision: https://reviews.llvm.org/D43170


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325030 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-13 18:00:25 +00:00
Matt Arsenault
6f2da0b6ad Reapply "AMDGPU: Add 32-bit constant address space"
This reverts r324494 and reapplies r324487.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324747 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-09 16:57:57 +00:00
Yaxun Liu
a43548c056 [AMDGPU] Updae documentation about address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324617 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-08 15:41:19 +00:00
Rafael Espindola
c952538085 Revert "AMDGPU: Add 32-bit constant address space"
This reverts commit r324487.

It broke clang tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324494 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-07 18:09:35 +00:00
Marek Olsak
3afd566557 AMDGPU: Add 32-bit constant address space
Note: This is a candidate for LLVM 6.0, because it was planned to be
      in that release but was delayed due to a long review period.

Merge conflict in release_60 - resolution:
    Add "-p6:32:32" into the second (non-amdgiz) string.

Only scalar loads support 32-bit pointers. An address in a VGPR will
fail to compile. That's OK because the results of loads will only be used
in places where VGPRs are forbidden.

Updated AMDGPUAliasAnalysis and used SReg_64_XEXEC.
The tests cover all uses cases we need for Mesa.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D41651

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324487 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-07 16:01:00 +00:00
Tony Tye
90018a5eac [AMDGPU] Update relocation documentation and elf flag machine architecture numbers
Differential Revision: https://reviews.llvm.org/D42714


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323835 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-30 23:59:43 +00:00
Tony Tye
ae5d34e5ef [AMDGPU] Clarify ReqdWorkGroupSize and MaxFlatWorkGroupSize metadata
- If ReqdWorkGroupSize is present it must have all elements >=1.
- If MaxFlatWorkGroupSize must be consistent with ReqdWorkGroupSize.
- Remove FixedWorkGroupSize as now equivalent to ReqdWorkGroupSize.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323829 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-30 23:07:10 +00:00
Tim Hammerquist
4967d786bb fix invalid footnote syntax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321839 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-05 00:24:54 +00:00