Commit Graph

6 Commits

Author SHA1 Message Date
Francis Visoiu Mistrih bea0f24e1c [MIR] Add support for debug metadata for fixed stack objects
Debug var, expr and loc were only supported for non-fixed stack objects.

This patch adds the following fields to the "fixedStack:" entries, and
renames the ones from "stack:" to:

* debug-info-variable
* debug-info-expression
* debug-info-location

Differential Revision: https://reviews.llvm.org/D46032

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330859 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 18:58:06 +00:00
Puyan Lotfi 1076969bfe Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323922 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-31 22:04:26 +00:00
Justin Bogner edab757966 MIR: Print the register class or bank in vreg defs
This updates the MIRPrinter to include the regclass when printing
virtual register defs, which is already valid syntax for the
parser. That is, given 64 bit %0 and %1 in a "gpr" regbank,

  %1(s64) = COPY %0(s64)

would now be written as

  %1:gpr(s64) = COPY %0(s64)

While this change alone introduces a bit of redundancy with the
registers block, it allows us to update the tests to be more concise
and understandable and brings us closer to being able to remove the
registers block completely.

Note: We generally only print the class in defs, but there is one
exception. If there are uses without any defs whatsoever, we'll print
the class on all uses. I'm not completely convinced this comes up in
meaningful machine IR, but for now the MIRParser and MachineVerifier
both accept that kind of stuff, so we don't want to have a situation
where we can print something we can't parse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24 18:04:54 +00:00
Matt Arsenault ec61af4bcc AMDGPU: Fix crash on immediate operand
We can have a v_mac with an immediate src0.
We can still fold if it's an inline immediate,
otherwise it already uses the constant bus.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313852 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-21 00:45:59 +00:00
Matt Arsenault 11283fb2c8 AMDGPU: Fix violating constant bus restriction
You can't use madmk/madmk if it already uses an SGPR input.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313298 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-14 20:54:29 +00:00
Stanislav Mekhanoshin 46582be974 [AMDGPU] Produce madak and madmk from the two-address pass
These two instructions are normally selected, but when the
two address pass converts mac into mad we end up with the
mad where we could have one of these.

Differential Revision: https://reviews.llvm.org/D37389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312928 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-11 17:13:57 +00:00