Commit Graph

25800 Commits

Author SHA1 Message Date
Akira Hatanaka
88373c29fe [mips] Use register operands instead of register classes in DSP instruction
definitions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 01:02:20 +00:00
Akira Hatanaka
7d6355226c [mips] Rename DSPRegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188342 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:53:38 +00:00
Akira Hatanaka
cbaf6d0cc3 [mips] Rename HIRegs and LORegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:47:08 +00:00
Akira Hatanaka
bfb07b1054 [mips] Properly parse registers that appear in inline-asm constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:21:25 +00:00
Jack Carter
3f70e908c3 [Mips][msa] Added initial MSA support.
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 20:54:07 +00:00
Jack Carter
da0860f78e [Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 20:19:16 +00:00
Michael Gottesman
3add0679d2 Update makeLibCall to return both the call and the chain associated with the libcall instead of just the call. This allows us to specify libcalls that return void.
LowerCallTo returns a pair with the return value of the call as the first
element and the chain associated with the return value as the second element. If
we lower a call that has a void return value, LowerCallTo returns an SDValue
with a NULL SDNode and the chain for the call. Thus makeLibCall by just
returning the first value makes it impossible for you to set up the chain so
that the call is not eliminated as dead code.

I also updated all references to makeLibCall to reflect the new return type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188300 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 17:54:56 +00:00
Joey Gouly
3f87f2510c ARMv8: SWP and SWPB are obsoleted on ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 16:40:47 +00:00
Evgeniy Stepanov
4c857225ec Fix compiler warnings.
../lib/Target/X86/X86ISelLowering.cpp:9715:7: error: unused variable 'OpVT' [-Werror,-Wunused-variable]
  EVT OpVT = Op0.getValueType();
      ^
../lib/Target/X86/X86ISelLowering.cpp:9763:14: error: unused variable 'NumElems' [-Werror,-Wunused-variable]
    unsigned NumElems = VT.getVectorNumElements();



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 14:04:20 +00:00
Mihai Popa
ea8ddd86b1 Fix signed overflow in when computing encodings for ADR instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 14:02:13 +00:00
Elena Demikhovsky
4d36bd80e6 AVX-512: Added CMP and BLEND instructions.
Lowering for SETCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 13:24:07 +00:00
Vladimir Medic
bd980e5569 This patch introduces changes to MipsAsmParser register parsing routines. The code now follows more deterministic path and makes the code more efficient and easier to maintain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 13:07:09 +00:00
Kevin Enderby
ebc573ed5b Fix a crash with X86 Mach-O and a subtraction expression where both symbols are
undefined and produce an error message instead as this is a non-relocatable
expression with X86 Mach-O.

rdar://8920876


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188218 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 22:45:44 +00:00
Tom Stellard
f15dfe4eb4 R600: Set scheduling preference to Sched::Source
R600 doesn't need to do any scheduling on the SelectionDAG now that it
has a very good MachineScheduler.  Also, using the VLIW SelectionDAG
scheduler was having a major impact on compile times. For example with
the phatk kernel here are the LLVM IR to machine code compile times:

With Sched::VLIW

Total Compile Time:                  1.4890 Seconds (User + System)
SelectionDAG Instruction Scheduling: 1.1670 Seconds (User + System)

With Sched::Source

Total Compile Time:                  0.3330 Seconds (User + System)
SelectionDAG Instruction Scheduling: 0.0070 Seconds (User + System)

The code ouput was identical with both schedulers.  This may not be true
for all programs, but it gives me confidence that there won't be much
reduction, if any, in code quality by using Sched::Source.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 22:33:21 +00:00
Vladimir Medic
809313970f This patch implements ei and di instructions for mips. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 13:07:23 +00:00
Richard Sandiford
ac168b8bc8 [SystemZ] Use CLC and IPM to implement memcmp
For now this is restricted to fixed-length comparisons with a length
in the range [1, 256], as for memcpy() and MVC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188163 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 10:28:10 +00:00
Richard Sandiford
e03a56d62f [SystemZ] Add a definition of the CLC instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 10:17:33 +00:00
Richard Sandiford
f37c8feb46 [SystemZ] Add a definition of the IPM instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 10:05:58 +00:00
Benjamin Kramer
674c91bb6e Remove global construction. const char* is sufficient here.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188158 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 09:37:29 +00:00
Reed Kotler
5e4b95b3fe Don't generate floating point stubs for mips16 code if the function
is actually an instrinsic that will not occur in libc. This list here
is not exhaustive but fixes the one places in test-suite where this occurs.
I have filed a bug against myself to research the full list and add them
to the array of such cases. In the future, actual stub generation will occur
in a later phase and we won't need this code because we will know at that time
during the compilation that in fact no helper function was even needed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188149 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-11 21:30:27 +00:00
Elena Demikhovsky
55db69c97e AVX-512: Added more tests for BROADCAST
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-11 12:29:16 +00:00
Elena Demikhovsky
fac4a4eb7d AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions.
Added a test for shuffles using VPERM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-11 07:55:09 +00:00
Reed Kotler
76ba4f5275 Incorrect JAL instruction attributes caused the optimizer to make a wrong
instruction move. Just affects static relocation. -static works fine now
with mips16 for the most part.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-10 22:18:22 +00:00
Venkatraman Govindaraju
d8de58e24c [Sparc] Enable xword directive in sparcv9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-10 20:13:20 +00:00
Niels Ole Salscheider
6e4dbcd115 R600/SI: FMA is faster than fmul and fadd for f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-10 10:38:54 +00:00
Niels Ole Salscheider
4ab92e4d4b R600/SI: Add FMA pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-10 10:38:47 +00:00
Reed Kotler
1e07de3529 Add another intrinsic that LLVM gives an incorrect prototype to.
I need to go through all the runtime routine list and see if there
are any more I need to add for mips16 floating point. Prototypes must
be correct or else I don't know to add a helper function call.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 21:33:41 +00:00
Benjamin Kramer
fc6434a73d Add a overload to CostTable which allows it to infer the size of the table.
Use it to avoid repeating ourselves too often. Also store MVT::SimpleValueType
in the TTI tables so they can be statically initialized, MVT's constructors
create bloated initialization code otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188095 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 19:33:32 +00:00
Mihai Popa
04b03fac11 This fixes the Thumb2 CPS assembly syntax.
In Thumb1, only one variant is supported: CPS{effect} {flags}

Thumb2 supports three:
CPS{effect}.W {flags}
CPS{effect} {flags} {mode}
CPS {mode}

Canonically, .W should be used only when ambiguity is present between encodings of different width.
The wide suffix is still accepted for the latter two forms via aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 13:52:32 +00:00
Mihai Popa
e921f32353 Fix assembling of Thumb2 branch instructions.
The long encoding for Thumb2 unconditional branches is broken.
Additionally, there is no range checking for target operands; as such 
for instructions originating in assembly code, only short Thumb encodings
are generated, regardless of the bitsize needed for the offset.

Adding range checking is non trivial due to the representation of Thumb
branch instructions. There is no true difference between conditional and
unconditional branches in terms of operands and syntax - even unconditional
branches have a predicate which is expected to match that of the IT block
they are in. Yet, the encodings and the permitted size of the offset differ.

Due to this, for any mnemonic there are really 4 encodings to choose for.

The problem cannot be handled in the parser alone or by manipulating td files.
Because the parser builds first a set of match candidates and then checks them
one by one, whatever tablegen-only solution might be found will ultimately be
dependent of the parser's evaluation order. What's worse is that due to the fact
that all branches have the same syntax and the same kinds of operands, that 
order is governed by the lexicographical ordering of the names of operand 
classes...

To circumvent all this, any necessary disambiguation is added to the instruction
validation pass.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 10:38:32 +00:00
Richard Sandiford
6514751d12 [SystemZ] Update README
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188062 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-09 09:25:57 +00:00
Jack Carter
d12fce1a27 Mips ELF: MicroMips direct object Little endian support.
Test included.

Patch by Zoran Jovanovich


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188024 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 23:30:40 +00:00
Michael J. Spencer
081a1941b5 [Object] Split the ELF interface into 3 parts.
* ELFTypes.h contains template magic for defining types based on endianess, size, and alignment.
* ELFFile.h defines the ELFFile class which provides low level ELF specific access.
* ELFObjectFile.h contains ELFObjectFile which uses ELFFile to implement the ObjectFile interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188022 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 22:27:13 +00:00
Akira Hatanaka
491d04969d [mips] Rename accumulator register classes and FP register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:54:26 +00:00
Akira Hatanaka
7af40bfa66 [mips] Mark pseudo instructions as code-gen only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188017 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:44:39 +00:00
Akira Hatanaka
94a88c49b0 [mips] Delete register class HWRegs64.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:37:32 +00:00
David Fang
d76adee1b2 cast fix to appease buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:29:30 +00:00
David Fang
d4f9d05fde initial draft of PPCMachObjectWriter.cpp
this records relocation entries in the mach-o object file
for PIC code generation.
tested on powerpc-darwin8, validated against darwin otool -rvV

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188004 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 20:14:40 +00:00
Niels Ole Salscheider
014773626d R600/SI: Implement fp32<->fp64 conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 16:06:15 +00:00
Niels Ole Salscheider
7114e2e7cf R600/SI: Implement sint<->fp64 conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 16:06:08 +00:00
Jakub Staszak
91955e78e7 Use pop_back() instead of pop_back_val() when the returned value is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 15:48:46 +00:00
Silviu Baranga
cee3538233 Remove the now redundant FeatureFP16 from the Cortex-A15 feature list. It was made redundant when FeatureVFP4 was added which implies FP16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 15:47:33 +00:00
Jakub Staszak
72feef14f1 Fix the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 15:19:25 +00:00
Mihai Popa
868bed9967 The name "tCDP" isn't used anywhere else in the source code, so renaming it for consistency doesn't cause any problems.
This is the only Thumb2 instruction defined with "t" prefix; all other Thumb2 instructions have "t2" prefix (e.g. "t2CDP2" which is defined immediately afterwards).

Patch by Artyom Skrobov.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 10:20:41 +00:00
Hal Finkel
05a4d2642b PPC: Map frin to round() not nearbyint() and rint()
Making use of the recently-added ISD::FROUND, which allows for custom lowering
of round(), the PPC backend will now map frin to round(). Previously, we had
been using frin to lower nearbyint() (and rint() via some custom lowering to
handle the extra fenv flags requirements), but only in fast-math mode because
frin does not tie-to-even. Several users had complained about this behavior,
and this new mapping of frin to round is certainly more appropriate (and does
not require fast-math mode).

In effect, this reverts r178362 (and part of r178337, replacing the nearbyint
mapping with the round mapping).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187960 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 04:31:34 +00:00
Hal Finkel
41418d17cc Add ISD::FROUND for libm round()
All libm floating-point rounding functions, except for round(), had their own
ISD nodes. Recent PowerPC cores have an instruction for round(), and so here I'm
adding ISD::FROUND so that round() can be custom lowered as well.

For the most part, this is straightforward. I've added an intrinsic
and a matching ISD node just like those for nearbyint() and friends. The
SelectionDAG pattern I've named frnd (because ISD::FP_ROUND has already claimed
fround).

This will be used by the PowerPC backend in a follow-up commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187926 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 22:49:12 +00:00
Elena Demikhovsky
207600d2cf AVX-512 set: Added BROADCAST instructions
with lowering logic and a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 12:34:55 +00:00
Richard Sandiford
29e873ddb6 [SystemZ] Optimize floating-point comparisons with zero
This follows the same lines as the integer code.  In the end it seemed
easier to have a second 4-bit mask in TSFlags to specify the compare-like
CC values.  That eats one more TSFlags bit than adding a CCHasUnordered
would have done, but it feels more concise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187883 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 11:10:06 +00:00
Richard Sandiford
e0bbf7288c [SystemZ] Add floating-point load-and-test instructions
These instructions can also be used as comparisons with zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 11:03:34 +00:00
Craig Topper
b19982c42b Simplify code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187870 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 08:16:07 +00:00