153651 Commits

Author SHA1 Message Date
Davide Italiano
ce5cab1140 [Inliner] Only compute fully inline cost when remarks are enabled.
Prior to this change (and after r311371), we computed it
unconditionally, causin gsevere compile time regressions (in some
cases, 5 to 10x).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311804 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 22:01:42 +00:00
Matt Morehouse
cd698b8c34 Revert "[SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzer"
This reverts r311801 due to a bot failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311803 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 22:01:21 +00:00
Matt Morehouse
8d5696051c [SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzer
Summary:
- Don't sanitize __sancov_lowest_stack.
- Don't instrument leaf functions.
- Add CoverageStackDepth to Fuzzer and FuzzerNoLink.

Reviewers: vitalybuka, kcc

Reviewed By: kcc

Subscribers: cfe-commits, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D37156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311801 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 21:18:29 +00:00
Sanjay Patel
34ce329ff4 [utils] add aarch64 target as an option
I don't know enough to add a custom scrubber for AArch64, so I just re-used ARM.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311795 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 19:33:18 +00:00
Kostya Serebryany
df54667cf4 [sanitizer-coverage] extend fsanitize-coverage=pc-table with flags for every PC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311794 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 19:29:47 +00:00
Sanjay Patel
0588b413e4 [x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311793 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 19:25:03 +00:00
Haicheng Wu
33be26f893 [InlineCost] Small changes to early exit condition. NFC.
Change the early exit condition from Cost > Threshold to Cost >= Threshold
because the inline condition is Cost < Threshold.

Differential Revision: https://reviews.llvm.org/D37087

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311791 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 19:00:33 +00:00
Craig Topper
ef9c2d804e [InstCombine] Don't fall back to only calling computeKnownBits if the upper bit of Add/Sub is demanded.
Just create an all 1s demanded mask and continue recursing like normal. The recursive calls should be able to handle an all 1s mask and do the right thing.

The only time we should care about knowing whether the upper bit was demanded is when we need to know if we should clear the NSW/NUW flags.

Now that we have a consistent path through the code for all cases, use KnownBits::computeForAddSub to compute the known bits at the end since we already have the LHS and RHS.

My larger goal here is to move the code that turns add into xor if only 1 bit is demanded and no bits below it are non-zero from InstCombiner::OptAndOp to here. This will allow it to be more general instead of just looking for 'add' and 'and' with constant RHS.

Differential Revision: https://reviews.llvm.org/D36486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311789 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 18:39:40 +00:00
Craig Topper
3ec9576f37 [InstCombine] Add tests to show missed opportunities to combine bit tests hidden by a sign compare and a truncate. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311784 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 17:14:35 +00:00
Florian Hahn
f360477df5 [LoopInterchange] Skip zext instructions when looking for induction var.
Summary:
SimplifyIndVar may introduce zext instructions to widen arguments of the
loop exit check. They should not prevent us from splitting the loop at
the induction variable, but maybe the check should be more conservative,
e.g. making sure it only extends arguments used by a comparison?

Reviewers: karthikthecool, mcrosier, mzolotukhin

Reviewed By: mcrosier

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D34879

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311783 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 16:52:29 +00:00
David Blaikie
7cd5c43854 Fix unused-lambda-capture warning by using default capture-by-ref
Since the lambda isn't escaped (via a std::function or similar) it's
fine/better to use default capture-by-ref to provide semantics similar
to language-level nested scopes (if/for/while/etc).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311782 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 16:46:07 +00:00
Matt Morehouse
2cfe1040ad Fix buildbot breakage from r311763. Remove unused lambda capture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311781 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 16:19:26 +00:00
David Green
6e7a4adfcf [gold] Fix up a new test to allow it to pass on non x86 builds.
Fix a test that is failing on a downstream ARM/AArch64
bootstrap. We just need add an elf_x86_64 parameter to
gold.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311780 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 16:14:56 +00:00
Michael Kruse
f29303de23 Normlize to LF line endings.
Commit r297442 introduced mixed CRLF/LF line endings to two files.
Normalize to to LF-only line endings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311774 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 12:38:53 +00:00
Amjad Aboud
513af851dd [InstCombine] Consider more cases where SimplifyDemandedUseBits does not convert AShr to LShr.
There are cases where AShr have better chance to be optimized than LShr, especially when the demanded bits are not known to be Zero, and also known to be similar to the sign bit.

Differential Revision: https://reviews.llvm.org/D36936




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311773 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 11:07:54 +00:00
Ilya Biryukov
33badf7093 Use temporary directory when building docker image.
Summary:
This avoids races on copying of compiled clang from 'build' image
to 'release' image.

Reviewers: klimek, mehdi_amini

Reviewed By: mehdi_amini

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37098

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311769 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 09:03:57 +00:00
Craig Topper
bbcf25671b [X86] Use SDValue::getOpcode instead of calling getNode and calling getOpcode on that. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311765 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 05:36:29 +00:00
Craig Topper
bfd106e576 [X86] Use isUInt and isShiftedUInt instead of using our own masking and compares. NFCI
While there use a local variable instead of calling C->getZExtValue() repeatedly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311764 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 05:04:34 +00:00
Aditya Nandakumar
43aeabcde1 [GISel]: Implement widenScalar for Legalizing G_PHI
https://reviews.llvm.org/D37018

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311763 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 04:57:27 +00:00
Chandler Carruth
20943fdc57 [x86] NFC - normalize test case formatting of IR and generate CHECK
lines with the script rather than using manually written checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311753 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 02:32:51 +00:00
Chandler Carruth
2b7d94b2dc Teach the llc check updater to recognize the end-of-function comment
used on Windows and sometimes Darwin. Cleans up generated patterns for
me quite a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311752 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 02:32:48 +00:00
Gor Nishanov
8970bfadd2 [coroutines] Add support for symmetric control transfer (musttail on coro.resumes followed by a suspend)
Summary:
Add musttail to any resume instructions that is immediately followed by a
suspend (i.e. ret). We do this even in -O0 to support guaranteed tail call
for symmetrical coroutine control transfer (C++ Coroutines TS extension).
This transformation is done only in the resume part of the coroutine that has
identical signature and calling convention as the coro.resume call.

Reviewers: GorNishanov

Reviewed By: GorNishanov

Subscribers: EricWF, majnemer, llvm-commits

Differential Revision: https://reviews.llvm.org/D37125

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311751 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 02:25:10 +00:00
Chandler Carruth
5872ccc628 [x86] NFC: More refactoring to pave the way to extending this ISel logic
to handle other x86 pseudos that carry flags and thus can't be matched
by our ISel patterns with fused memory accesses.

Differential Revision: https://reviews.llvm.org/D37088

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311749 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 02:06:36 +00:00
Chandler Carruth
22db2c96fb [x86] NFC - Refactor the custom lowering of (load; op; store) RMW sequences.
This extracts the code out of a giant switch in preparation for expanding it to
handle operations other thin `inc` and `dec`. Add a FIXME indicating what's
coming here.

Differential Revision: https://reviews.llvm.org/D37045

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311748 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 02:04:03 +00:00
Craig Topper
01fd7ebe93 [X86] Add TBM instructions to X86InstrInfo::isDefConvertible.
This allows us to remove "test" instructions and use the flags from the TBM instructions directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311747 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 01:59:06 +00:00
Matt Arsenault
88b89edf99 DAG: Fix naming crime
Because isOperationCustom was only checking for custom
lowering on illegal types, this was behaving inconsistently
with the other isOperation* functions, so that
isOperationLegalOrCustom != (isOperationLegal || isOperationCustom)

Luckily this is only used in one place which already checks the
type legality on its own.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311743 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 01:26:13 +00:00
Justin Bogner
965445287b [sanitizer-coverage] Make sure pc-tables aren't dead stripped
Add a reference to the PC array in llvm.used so that linkers that
aggressively dead strip (like ld64) don't remove it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311742 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 01:24:54 +00:00
Mandeep Singh Grang
109cbe502f [unittests] Remove reverse iteration tests which use pointer-like keys
Summary: The expected order of pointer-like keys is hash-function-dependent which in turn depends on the platform/environment. Need to come up with a better way to test reverse iteration of containers with pointer-like keys.

Reviewers: dblaikie, mehdi_amini, efriedma, mgrang

Reviewed By: mgrang

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37128

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311741 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 01:11:28 +00:00
Chandler Carruth
31f4977889 [x86] Back out one aspect of r311318: don't generically set
FeatureSlowUAMem32.

The idea was to mark things that are slow on widely available processors
as slow in the generic CPU so that the code generated for that CPU would
be fast across those processors. However, for this feature that doesn't
work out very well at all.

The problem here is that you can very easily enable AVX or AVX2 on top
of this generic CPU. For example, this can happen just by using AVX2
intrinsics from Clang within a region of code guarded by a dynamic CPU
feature test. When you do that, the generated code with SlowUAMem32 set
is ... amazingly slower. The problem is that there really aren't very
good alternatives to the unaligned loads, and so our vector codegen
regresses significantly.

The other issue is that there are plenty of AMD CPUs with AVX1 that
don't set FeatureSlowUAMem32 and so we shouldn't just check for AVX2
instead of this special feature. =/

It would be nice to have the target attriute logic be able to
enable/disable more than just one feature at a time and control this in
a more fine grained and useful way, but that doesn't seem easy. Given
that it is only Sandybridge and Ivybridge that set this feature, for now
I'm just backing it out of the generic CPU. That has the additional
advantage of going back to the previous state that people seemed vaguely
happy with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311740 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 00:56:05 +00:00
Stephen Hines
c2588cb4b1 Fix two (three) more issues with unchecked Error.
Summary:
If assertions are disabled, but LLVM_ABI_BREAKING_CHANGES is enabled,
this will cause an issue with an unchecked Success. Switching to
consumeError() is the correct way to bypass the check. This patch also
includes disabling 2 tests that can't work without assertions enabled,
since llvm_unreachable() with NDEBUG won't crash.

Reviewers: llvm-commits, lhames

Reviewed By: lhames

Subscribers: lhames, pirama

Differential Revision: https://reviews.llvm.org/D36729

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311739 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 00:48:21 +00:00
Chandler Carruth
66f94c748f [x86] Fix an amazing goof in the handling of sub, or, and xor lowering.
The comment for this code indicated that it should work similar to our
handling of add lowering above: if we see uses of an instruction other
than flag usage and store usage, it tries to avoid the specialized
X86ISD::* nodes that are designed for flag+op modeling and emits an
explicit test.

Problem is, only the add case actually did this. In all the other cases,
the logic was incomplete and inverted. Any time the value was used by
a store, we bailed on the specialized X86ISD node. All of this appears
to have been historical where we had different logic here. =/

Turns out, we have quite a few patterns designed around these nodes. We
should actually form them. I fixed the code to match what we do for add,
and it has quite a positive effect just within some of our test cases.
The only thing close to a regression I see is using:

  notl %r
  testl %r, %r

instead of:

  xorl -1, %r

But we can add a pattern or something to fold that back out. The
improvements seem more than worth this.

I've also worked with Craig to update the comments to no longer be
actively contradicted by the code. =[ Some of this still remains
a mystery to both Craig and myself, but this seems like a large step in
the direction of consistency and slightly more accurate comments.

Many thanks to Craig for help figuring out this nasty stuff.

Differential Revision: https://reviews.llvm.org/D37096

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311737 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-25 00:34:07 +00:00
Sanjay Patel
c8f9cf9e26 [DAG] convert vector select-of-constants to logic/math
This goes back to a discussion about IR canonicalization. We'd like to preserve and convert
more IR to 'select' than we currently do because that's likely the best choice in IR:
http://lists.llvm.org/pipermail/llvm-dev/2016-September/105335.html
...but that's often not true for codegen, so we need to account for this pattern coming in
to the backend and transform it to better DAG ops.

Steps in this patch:

  1. Add an EVT param to the existing convertSelectOfConstantsToMath() TLI hook to more finely
     enable this transform. Other targets will probably want that anyway to distinguish scalars
     from vectors. We're using that here to exclude AVX512 targets, but it may not be necessary.

  2. Convert a vselect to ext+add. This eliminates a constant load/materialization, and the
     vector ext is often free.

Implementing a more general fold using xor+and can be a follow-up for targets that don't have
a legal vselect. It's also possible that we can remove the TLI hook for the special case fold
implemented here because we're eliminating a constant, but it needs to be tested on other
targets.

Differential Revision: https://reviews.llvm.org/D36840



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311731 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 23:24:43 +00:00
Mandeep Singh Grang
89c6743f22 [ADT] Enable reverse iteration for DenseMap
Reviewers: mehdi_amini, dexonsmith, dblaikie, davide, chandlerc, davidxl, echristo, efriedma

Reviewed By: dblaikie

Subscribers: rsmith, mgorny, emaste, llvm-commits

Differential Revision: https://reviews.llvm.org/D35043

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311730 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 23:02:48 +00:00
Xinliang David Li
092c93330a [Profile] backward propagate profile info in JumpThreading
Take-2 after fixing bugs in the original patch.

Differential Revsion: http://reviews.llvm.org/D36864


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311727 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 22:54:01 +00:00
Sanjay Patel
3ff3073768 [InstCombine] fix and enhance udiv/urem narrowing
There are 3 small independent changes here:

  1. Account for multiple uses in the pattern matching: avoid the transform if it increases the instruction count.
  2. Add a missing fold for the case where the numerator is the constant: http://rise4fun.com/Alive/E2p
  3. Enable all folds for vector types.

There's still one more potential change - use "shouldChangeType()" to keep from transforming to an illegal integer type.

Differential Revision: https://reviews.llvm.org/D36988


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311726 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 22:54:01 +00:00
Dehao Chen
d38687abb5 Move accurate-sample-profile into the function attribute.
Summary: We need to have accurate-sample-profile in function attribute so that it works with LTO.

Reviewers: davidxl, rsmith

Reviewed By: davidxl

Subscribers: sanjoy, mehdi_amini, javed.absar, llvm-commits, eraman

Differential Revision: https://reviews.llvm.org/D37113

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311706 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 21:37:04 +00:00
Eugene Zelenko
2de563a9ab [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311703 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 21:21:39 +00:00
Chad Rosier
ca52e12050 [PartialInlining] Formatting. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311702 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 21:21:09 +00:00
Nathan Hawes
71f4afc0b8 test commit: fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311701 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 21:20:41 +00:00
Chad Rosier
8209cdfb4c [PartialInlining] Type. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311699 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 20:29:02 +00:00
Konstantin Zhuravlyov
a698ffcfb3 AMDGPU: Fix gfx801 features
gfx801 has 1/2 rate F64, Fast F32 FMA

Differential Revision: https://reviews.llvm.org/D36981


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311694 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 20:03:07 +00:00
Jacob Gravelle
73e192592e [WebAssembly] FastISel : Bail to SelectionDAG for constexpr calls
Summary: Currently FastISel lowers constexpr calls as indirect calls.
We'd like those to direct calls, and falling back to SelectionDAGISel
handles that.

Reviewers: dschuff, sunfish

Subscribers: jfb, sbc100, llvm-commits, aheejin

Differential Revision: https://reviews.llvm.org/D37073

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311693 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 19:53:44 +00:00
Heejin Ahn
3133c0dc5b [WebAssembly] Update GCC test suite failure expectations
Summary:
Update GCC test suite failure expectations as we add -O0 to the bare tests in
WebAssembly waterfall. There are still several untriaged lld failures.

Reviewers: sbc100, jgravelle-google, dschuff

Reviewed By: dschuff

Subscribers: jfb

Differential Revision: https://reviews.llvm.org/D37100

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311691 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 19:43:09 +00:00
Krzysztof Parzyszek
c20cb18c00 [Hexagon] Set access size for vector pseudo loads/stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311690 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 19:19:24 +00:00
Daniel Sanders
a8273d0212 [globalisel][tablegen] Predicates should start from GIPFP_Invalid+1 not GIPFP_Invalid
This fixes a warning when there are zero defined predicates and also fixes an
unnoticed bug where the first predicate in the table was unusable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311684 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 18:54:16 +00:00
Victor Leschuk
e34366cdd6 Remove duplicate code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311675 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 17:02:38 +00:00
Victor Leschuk
b9f31ca1b8 Add missing break in switch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311673 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 16:57:10 +00:00
Pete Couperus
53355ce574 [ARC] Add ARC backend.
Add the ARC backend as an experimental target to lib/Target.
Reviewed at: https://reviews.llvm.org/D36331



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311667 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 15:40:33 +00:00
Krasimir Georgiev
f372a9f69a [X86AsmParser] Refactor AsmRewrite constructors, NFCI
Summary:
This is a follow-up of https://reviews.llvm.org/D37105, where a slight refactoring
of the constructors of AsmRewrite is proposed.

Reviewers: coby

Reviewed By: coby

Differential Revision: https://reviews.llvm.org/D37110

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311666 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 15:03:18 +00:00
Sanjay Patel
616b6cc126 fix typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-24 15:00:13 +00:00