2 Commits

Author	SHA1	Message	Date
QingShan Zhang	12df467aac	[PowerPC] Add a peephole post RA to transform the inst that fed by add ... If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340149 91177308-0d34-0410-b5e6-96231b3b80d8	2018-08-20 02:52:55 +00:00
QingShan Zhang	21cf43199f	If the arch is P9, we will select the DFLOADf32/DFLOADf64 pseudo instruction when we are loading a floating, ... and expand it post RA basing on the register pressure. However, we miss to do the add-imm peephole for these pseudo instruction. Differential Revision: https://reviews.llvm.org/D47568 Reviewed By: Nemanjai git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335024 91177308-0d34-0410-b5e6-96231b3b80d8	2018-06-19 06:54:51 +00:00