Commit Graph

9 Commits

Author SHA1 Message Date
Ahmed Bougacha
4c690f3954 [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.
This re-applies r268760, reverted in r268794.
Fixes http://llvm.org/PR27670

The original imp-defs assertion was way overzealous: forward all
implicit operands, except imp-defs of the new super-reg def (r268787
for GR64, but also possible for GR16->GR32), or imp-uses of the new
super-reg use.
While there, mark the source use as Undef, and add an imp-use of the
old source reg: that should cover any case of dead super-regs.

At the stage the pass runs, flags are unlikely to matter anyway;
still, let's be as correct as possible.

Also add MIR tests for the various interesting cases.

Original commit message:
Codesize is less (16) or equal (8), and we avoid partial
dependencies.

Differential Revision: http://reviews.llvm.org/D19999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268831 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-07 01:11:17 +00:00
Nico Weber
a019a2c0f5 Revert r268760, it caused PR27670.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268794 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-06 21:07:02 +00:00
Ahmed Bougacha
292650f3ea [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.
Codesize is less (16) or equal (8), and we avoid partial dependencies.

Differential Revision: http://reviews.llvm.org/D19999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268760 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-06 17:42:57 +00:00
Sanjay Patel
0969a1d57f fix CHECK_NEXT -> CHECK-NEXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264661 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-28 21:14:24 +00:00
Sanjay Patel
eb8298cfe1 [x86] enable machine combiner reassociations for scalar 'xor' insts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246781 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-03 16:36:16 +00:00
Sanjay Patel
63384be23d [x86] enable machine combiner reassociations for scalar 'or' insts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246481 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-31 20:27:03 +00:00
Sanjay Patel
4b1821fa36 [x86] enable machine combiner reassociations for scalar 'and' insts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246300 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-28 14:09:48 +00:00
Sanjay Patel
91add497c6 [x86] machine combiner reassociation: mark EFLAGS operand as 'dead'
In the commentary for D11660, I wasn't sure if it was alright to create new
integer machine instructions without also creating the implicit EFLAGS operand. 
From what I can see, the implicit operand is always created by the MachineInstrBuilder
based on the instruction type, so we don't have to do that explicitly. However, in
reviewing the debug output, I noticed that the operand was not marked as 'dead'. 
The machine combiner should do that to preserve future optimization opportunities 
that may be checking for that dead EFLAGS operand themselves.

Differential Revision: http://reviews.llvm.org/D11696


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243990 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-04 15:21:56 +00:00
Sanjay Patel
8ae0800ae1 [x86] reassociate integer multiplies using machine combiner pass
Add i16, i32, i64 imul machine instructions to the list of reassociation
candidates.

A new bit of logic is needed to handle integer instructions: they have an
implicit EFLAGS operand, so we have to make sure it's dead in order to do
any reassociation with integer ops.

Differential Revision: http://reviews.llvm.org/D11660



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243756 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 16:21:55 +00:00