Commit Graph

15 Commits

Author SHA1 Message Date
Sanjay Patel f033627be4 [x86] scalarize extract element 0 of FP cmp
An extension of D58282 noted in PR39665:
https://bugs.llvm.org/show_bug.cgi?id=39665

This doesn't answer the request to use movmsk, but that's an
independent problem. We need this and probably still need
scalarization of FP selects because we can't do that as a
target-independent transform (although it seems likely that
targets besides x86 should have this transform).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355741 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-08 21:54:41 +00:00
Craig Topper b375b52501 [X86] Change vXi1 extract_vector_elt lowering to be legal if the index is 0. Add DAG combine to turn scalar_to_vector+extract_vector_elt into extract_subvector.
We were lowering the last step extract_vector_elt to a bitcast+truncate. Change it to use an extract_vector_elt of index 0 instead. Add isel patterns to do the equivalent of what the bitcast would have done. Plus an isel pattern for an any_extend+extract to prevent some regressions.

Finally add a DAG combine to turn v1i1 scalar_to_vector+extract_vector_elt of 0 into an extract_subvector.

This fixes some of the regressions from D350800.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350918 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-11 05:44:56 +00:00
Craig Topper b6b44e8106 [X86] Disable DomainReassignment pass when AVX512BW is disabled to avoid injecting VK32/VK64 references into the MachineIR
Summary:
This pass replaces GR8/GR16/GR32/GR64 with their equivalent sized mask register classes. But VK32/VK64 aren't legal without AVX512BW. Apparently this mostly appears to work if the register coalescer is able to remove the VK32/VK64 register class reference. Or if we don't ever spill it. But there's no guarantee of that.

Another Intel employee managed to trigger a crash due to this with ISPC. Unfortunately, I've lost the test case he sent me at the time. I'm trying to get him to reproduce it for me. I'd like to get this in before 8.0 branches since its a little scary.

The regressions here are unfortunate, but I think we can make some improvements to DAG combine, load folding, etc. to fix them. Just not sure if we can get that done for 8.0.

Fixes PR39741

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D56460

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350800 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-10 07:43:54 +00:00
Craig Topper f3ae95d632 [X86] Force floating point values in constant pool decoding to print in scientific notation so they can't be confused with integers.
When the floating point constants are whole numbers they have no decimal point so look like integers, but mean something very different in something like an 'and' instruction.

Ideally we would just print a decimal point and a 0, but I couldn't see how to make APFloat::toString do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345488 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-29 04:52:04 +00:00
Simon Pilgrim 16b860b6ae [X86] Standardize floating point assembly comments
Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well.

Differential Revision: https://reviews.llvm.org/D52702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343562 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:08:51 +00:00
Craig Topper 54edf4671d [X86] Don't fold unaligned loads into SSE ROUNDPS/ROUNDPD for ceil/floor/nearbyint/rint/trunc.
Incorrect patterns were added in r334460. This changes them to check alignment properly for SSE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335062 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 17:51:42 +00:00
Mikhail Dvoretckii be59eb33a0 [X86] VRNDSCALE* folding from masked and scalar ffloor and fceil patterns
This patch handles back-end folding of generic patterns created by lowering the
X86 rounding intrinsics to native IR in cases where the instruction isn't a
straightforward packed values rounding operation, but a masked operation or a
scalar operation.

Differential Revision: https://reviews.llvm.org/D45203


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335037 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 10:37:52 +00:00
Craig Topper ebf3d94ea5 [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass.
Bits 7:4 control the scale part of the operation. If the scale is 0 the behavior is equivalent to VROUND.

Fixes PR36246

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324985 91177308-0d34-0410-b5e6-96231b3b80d8
2018-02-13 04:19:26 +00:00
Francis Visoiu Mistrih ca0df55065 [CodeGen] Unify MBB reference format in both MIR and debug output
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 17:18:51 +00:00
Craig Topper 6e10efc50e [X86] Use vrndscaleps/pd for 128/256 ffloor/ftrunc/fceil/fnearbyint/frint when avx512vl is enabled.
This matches what we do for scalar and 512-bit types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317991 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 21:44:51 +00:00
Craig Topper 1b52c8d11b [X86] Add avx512vl command line to vec_floor.ll. Add 512-bit test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317989 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 21:44:49 +00:00
Simon Pilgrim 44e6fffbb4 [X86][SSE] Regenerated vector float tests - fabs / floor(etc.) / fneg / float2double
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265186 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-01 21:30:48 +00:00
Simon Pilgrim 7d424d47d3 [DAGCombiner] Add support for FCEIL, FFLOOR and FTRUNC vector constant folding
Differential Revision: http://reviews.llvm.org/D8715

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234179 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-06 17:15:41 +00:00
Craig Topper d577552c66 Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168141 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16 06:37:56 +00:00
Craig Topper 12fb5c667f Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163473 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08 17:42:27 +00:00