10 Commits

Author SHA1 Message Date
Mehdi Amini
bf8318ccc8 [IPRA] Set callee saved registers to none for local function when IPRA is enabled.
IPRA try to optimize caller saved register by propagating register
usage information from callee to caller so it is beneficial to have
caller saved registers compare to callee saved registers when IPRA
is enabled. Please find more detailed explanation here
https://groups.google.com/d/msg/llvm-dev/XRzGhJ9wtZg/tjAJqb0eEgAJ.

This change makes local function do not have any callee preserved
register when IPRA is enabled. A simple test case is also added to
verify this change.

Patch by Vivek Pandya <vivekvpandya@gmail.com>

Differential Revision: http://reviews.llvm.org/D21561

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275347 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-13 23:39:34 +00:00
David Majnemer
700f7026c8 [CodeGen, TargetPassConfig] Remove a race from createRegAllocPass
The createRegAllocPass reads and writes to a global variable 'Registry'
via calls to getDefault and setDefault.  Run this under a call_once to
avoid races.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274875 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08 16:39:00 +00:00
George Burgess IV
3b5b98a488 [CFLAA] Split into Anders+Steens analysis.
StratifiedSets (as implemented) is very fast, but its accuracy is also
limited. If we take a more aggressive andersens-like approach, we can be
way more accurate, but we'll also end up being slower.

So, we've decided to split CFLAA into CFLSteensAA and CFLAndersAA.

Long-term, we want to end up in a place where CFLSteens is queried
first; if it can provide an answer, great (since queries are basically
map lookups). Otherwise, we'll fall back to CFLAnders, BasicAA, etc.

This patch splits everything out so we can try to do something like
that when we get a reasonable CFLAnders implementation.

Patch by Jia Chen.

Differential Revision: http://reviews.llvm.org/D21910


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274589 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-06 00:26:41 +00:00
Mehdi Amini
13c1e2501a Interprocedural Register Allocation (IPRA): add a Transformation Pass
Adds a MachineFunctionPass that scans the body to find calls, and
update the register mask with the one saved by the
RegUsageInfoCollector analysis in PhysicalRegisterUsageInfo.

Patch by Vivek Pandya <vivekvpandya@gmail.com>

Differential Revision: http://reviews.llvm.org/D21180

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272414 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-10 18:37:21 +00:00
Mehdi Amini
32b9ed845a Interprocedural Register Allocation (IPRA) Analysis
Add an option to enable the analysis of MachineFunction register
usage to extract the list of clobbered registers.

When enabled, the CodeGen order is changed to be bottom up on the Call
Graph.

The analysis is split in two parts, RegUsageInfoCollector is the
MachineFunction Pass that runs post-RA and collect the list of
clobbered registers to produce a register mask.

An immutable pass, RegisterUsageInfo, stores the RegMask produced by
RegUsageInfoCollector, and keep them available. A future tranformation
pass will use this information to update every call-sites after
instruction selection.

Patch by Vivek Pandya <vivekvpandya@gmail.com>

Differential Revision: http://reviews.llvm.org/D20769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272403 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-10 16:19:46 +00:00
Matt Arsenault
dcd25f4149 CodeGen: Allow verifier to run after MachineBlockPlacement
No tests break with this enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272340 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-09 23:31:55 +00:00
Matthias Braun
1cd242fe11 CodeGen: Refactor renameDisconnectedComponents() as a pass
Refactor LiveIntervals::renameDisconnectedComponents() to be a pass.
Also change the name to "RenameIndependentSubregs":

- renameDisconnectedComponents() worked on a MachineFunction at a time
  so it is a natural candidate for a machine function pass.

- The algorithm is testable with a .mir test now.

- This also fixes a problem where the lazy renaming as part of the
  MachineScheduler introduced IMPLICIT_DEF instructions after the number
  of a nodes in a region were counted leading to a mismatch.

Differential Revision: http://reviews.llvm.org/D20507

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271345 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 22:38:06 +00:00
Derek Schuff
4bfd3e29b1 Factor PrologEpilogInserter around spilling, frame finalization, and scavenging
PrologEpilogInserter has these 3 phases, which are related, but not
all of them are needed by all targets. This patch reorganizes PEI's
varous functions around those phases for more clear separation. It also
introduces a new TargetMachine hook, usesPhysRegsForPEI, which is true
for non-virtual targets. When it is true, all the phases operate as
before, and PEI requires the AllVRegsAllocated property on
MachineFunctions. Otherwise, CSR spilling and scavenging are skipped and
only prolog/epilog insertion/frame finalization is done.

Differential Revision: http://reviews.llvm.org/D18366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269750 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-17 08:49:59 +00:00
Matthias Braun
07636808ac TargetPassConfig: Set PrintMachineCode even if addMachinePasses() does not run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269013 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 04:51:04 +00:00
Matthias Braun
6a6190de10 CodeGen: Move TargetPassConfig from Passes.h to an own header; NFC
Many files include Passes.h but only a fraction needs to know about the
TargetPassConfig class. Move it into an own header. Also rename
Passes.cpp to TargetPassConfig.cpp while we are at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269011 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 03:21:59 +00:00