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3 Commits

Author SHA1 Message Date
Matt Arsenault
a3af6bb71d GlobalISel: Remove unsigned variant of SrcOp 
Force using Register.

One downside is the generated register enums require explicit
conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364194 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-24 16:16:12 +00:00
Matt Arsenault
a2b05bc24d CodeGen: Introduce a class for registers 
Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364191 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-06-24 15:50:29 +00:00
Tim Northover
14ed588ce0 CodeGen: factor out swifterror value tracking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361607 91177308-0d34-0410-b5e6-96231b3b80d8
 2019-05-24 08:39:43 +00:00