6 Commits

Author	SHA1	Message	Date
Simon Pilgrim	ead04a9559	[DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT ... If we are only extracting vector elements via EXTRACT_VECTOR_ELT(s) we may be able to use SimplifyDemandedVectorElts to avoid unnecessary vector ops. Differential Revision: https://reviews.llvm.org/D49262 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337258 91177308-0d34-0410-b5e6-96231b3b80d8	2018-07-17 09:45:35 +00:00
Simon Pilgrim	19f4c1ecb2	[ARM] Regenerated arg endian test ... As requested on D49262 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336980 91177308-0d34-0410-b5e6-96231b3b80d8	2018-07-13 09:16:56 +00:00
Justin Bogner	73773ce844	test/CodeGen: Check that the correct register is used in a store ... This tightens up r208351 to ensure that a store is fed with the correct value. Thanks to Quentin Colombet for spotting this! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208368 91177308-0d34-0410-b5e6-96231b3b80d8	2014-05-08 22:45:07 +00:00
Justin Bogner	8115f93cdb	Make a CodeGen test more robust against vector register selection ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208351 91177308-0d34-0410-b5e6-96231b3b80d8	2014-05-08 18:53:56 +00:00
Saleem Abdulrasool	f37151a2fd	test: fix test on Windows ... When building on Windows, the default target is Windows. Windows on ARM does not support ARM mode compilation, resulting in test failures. Simply specify a triple to ensure that we are testing the correct behaviour. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208340 91177308-0d34-0410-b5e6-96231b3b80d8	2014-05-08 17:11:29 +00:00
Christian Pirker	c60a59cad3	ARM big endian function argument passing ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208316 91177308-0d34-0410-b5e6-96231b3b80d8	2014-05-08 14:06:24 +00:00