RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-26 14:15:53 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
58,258 Commits 39 Branches 10 Tags 850 MiB
c7249da2e9
Commit Graph

34 Commits

Author SHA1 Message Date
Richard Osborne
d712783492 Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy. 
Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-26 16:44:51 +00:00
Richard Osborne
78700b0c55 Lower BR_JT on the XCore to a jump into a series of jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-23 13:25:07 +00:00
Chris Lattner
a34103f6fa convert the last 3 targets to use EmitFunctionBody() now that 
it has before/end body hooks.

 lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp |   49 ++-----------
 lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp   |   87 ++++++------------------
 lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp |   56 +++------------
 test/CodeGen/XCore/ashr.ll                      |    2 
 4 files changed, 48 insertions(+), 146 deletions(-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94741 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-28 06:22:43 +00:00
Dan Gohman
aceba31b7a Delete useless trailing semicolons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 17:55:26 +00:00
Richard Osborne
bea7df56ce Add XCore support for indirectbr / blockaddress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89273 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-18 23:20:42 +00:00
Richard Osborne
13c4fabf99 Add XCore support for arbitrary-sized aggregate returns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88802 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 19:33:35 +00:00
Richard Osborne
c96c8e0e81 Add some peepholes for signed comparisons using ashr X, X, 32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83549 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-08 15:38:17 +00:00
Dan Gohman
fce288fc91 Eliminate more uses of llvm-as and llvm-dis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-09 00:09:15 +00:00
Richard Osborne
1123135dbf Add support for mergeable sections back into the XCore backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79368 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-18 21:14:31 +00:00
Richard Osborne
a9e8334877 Put data with relocations in the same sections as data without relocations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79351 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-18 17:58:17 +00:00
Richard Osborne
2a5e23b44d Update getSectionForConstant() to to allow mergable sections to be nulled out 
if not supported by the ELF subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79249 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-17 16:37:11 +00:00
Chris Lattner
760e24cd05 use XCore-specific section with xcore specific cp/dp flags to restore 
support for globals going into the appropriate sections with the flags.

This hopefully finishes unbreaking the previous behavior that I broke before.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79079 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-15 06:09:35 +00:00
Richard Osborne
d558ea5e0a Add extra SEXT pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77920 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-02 22:45:24 +00:00
Chris Lattner
a87dea4f8c switch off of 'Section' onto MCSection. We're not properly using 
MCSection subclasses yet, but this is a step in the right direction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:48:30 +00:00
Richard Osborne
e23e0976c7 Add tests for handling of globals and tls on the XCore. These currently fail 
but pass when run against r76652.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76923 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:38:20 +00:00
Richard Osborne
db9e697725 Combine an unaligned store of unaligned load into a memmove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 12:50:48 +00:00
Richard Osborne
ccb7e96ef0 Expand unaligned 32 bit loads from an address which is a constant 
offset from a 32 bit aligned base as follows:

  ldw low, base[offset >> 2]
  ldw high, base[(offset >> 2) + 1]
  shr low_shifted, low, (offset & 0x3) * 8
  shl high_shifted, high, 32 - (offset & 0x3) * 8
  or result, low_shifted, high_shifted

Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:42:35 +00:00
Richard Osborne
7f47ce9662 Custom lower unaligned 32 bit stores and loads into libcalls. This is 
a big code size win since before they were expanding to upto 16
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75901 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-16 10:21:18 +00:00
Richard Osborne
1d05b237a5 Fix pattern for LD16S_3r, add basic tests to check load / store instructions 
are being properly selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75797 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 17:06:59 +00:00
Richard Osborne
3af282f16a Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75788 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-15 15:46:56 +00:00
Dan Gohman
ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate 
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-06-04 22:49:04 +00:00
Eli Friedman
2ac8b324eb Fix for PR4235: to build a floating-point value from integer parts, 
build an integer and cast that to a float.  This fixes a crash 
caused by trying to split an f32 into two f16's.

This changes the behavior in test/CodeGen/XCore/fneg.ll because that 
testcase now triggers a DAGCombine which converts the fneg into an integer
operation.  If someone is interested, it's probably possible to tweak 
the test to generate an actual fneg.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72162 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-20 06:02:09 +00:00
Chris Lattner
9dcab2fe8e testcase for PR3898 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69473 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-04-18 20:49:22 +00:00
Rafael Espindola
bb46f52027 Add the private linkage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-15 20:18:42 +00:00
Richard Osborne
cfb1ae87c6 Don't fold address calculations which use negative offsets into 
the ADDRspii addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62258 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-15 11:32:30 +00:00
Richard Osborne
29cab5f0ee Add pseudo instructions to the XCore for (load|store|load address) of a 
frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.

This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62238 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-14 18:26:46 +00:00
Richard Osborne
269bc0042f Add support for ISD::TRAP to the XCore backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60479 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-12-03 10:59:16 +00:00
Duncan Sands
51d83fdd89 Reapply r59464, this time using the correct type 
when softening FNEG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59513 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-18 09:15:03 +00:00
Bill Wendling
8f55b3d67d Revert r59464. It was causing this failure: 
Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/dg.exp ...
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll
Failed with signal(SIGABRT) at line 1
while running:  llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/test/CodeGen/XCore/fneg.ll |  llc -march=xcore > fneg.ll.tmp1.s
Assertion failed: (VT.isFloatingPoint() && "Cannot create integer FP constant!"), function getConstantFP, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/SelectionDAG.cpp, line 913.
0   llc                                 0x0092115c _ZN4llvm3sys18RemoveFileOnSignalERKNS0_4PathEPSs + 844
1   libSystem.B.dylib                   0x9217809b _sigtramp + 43
2   ???                                 0xffffffff 0x0 + 4294967295
3   libSystem.B.dylib                   0x921f0ec2 raise + 26
4   libSystem.B.dylib                   0x9220047f abort + 73
5   libSystem.B.dylib                   0x921f2063 __assert_rtn + 101
6   llc                                 0x005a5b0a _ZN4llvm12SelectionDAG13getConmake[1]: *** [check-local] Error 1
make: *** [check] Error 2



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59487 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-18 01:49:24 +00:00
Duncan Sands
7fed65a68d Add soft float support for a bunch more operations. Original 
patch by Richard Osborne, tweaked and extended by your humble
servant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59464 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-17 20:52:38 +00:00
Richard Osborne
104de6cf7b Don't produce ADDC/ADDE when expanding SHL unless they are legal 
for the target. This fixes PR3080.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59450 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-17 17:34:31 +00:00
Richard Osborne
223fd6efc8 [XCore] Fix expansion of 64 bit add/sub. Don't custom expand 
these operations if ladd/lsub are not available on the current
subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59305 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-14 15:59:19 +00:00
Richard Osborne
1d8f975890 Add XCore intrinsics for getid (returns thread id) and bitrev (reverses 
bits in a word).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59296 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-14 10:12:16 +00:00
Richard Osborne
b7ee8c4c1f Add basic test for XCore backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58841 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-11-07 11:24:12 +00:00