16902 Commits

Author SHA1 Message Date
Simon Pilgrim
c83e4f9067 [X86][SSE] Added non-temporal load tests for vector types
These currently lower to regular loads instead of MOVNTDQA

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271516 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-02 13:51:50 +00:00
Simon Pilgrim
22d789345f [X86][SSE] Replace (V)CVTTPS2DQ and VCVTTPD2DQ truncating (round to zero) f32/f64 to i32 with generic IR (llvm)
This patch removes the llvm intrinsics (V)CVTTPS2DQ and VCVTTPD2DQ truncation (round to zero) conversions and auto-upgrades to FP_TO_SINT calls instead.

Note: I looked at updating CVTTPD2DQ as well but this still requires a lot more work to correctly lower.

Differential Revision: http://reviews.llvm.org/D20860

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271510 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-02 10:55:21 +00:00
Sjoerd Meijer
feb0d0e38e This adds support for Cortex-A73 as an available target.
Differential Revision: http://reviews.llvm.org/D20865


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271508 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-02 10:48:52 +00:00
Craig Topper
f543143a73 [X86] Add AVX 256-bit load and stores to fast isel.
I'm not sure why this was missing for so long.

This also exposed that we were picking floating point 256-bit VMOVNTPS for some integer types in normal isel for AVX1 even though VMOVNTDQ is available. In practice it doesn't matter due to the execution dependency fix pass, but it required extra isel patterns. Fixing that in a follow up commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271481 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-02 04:19:45 +00:00
Craig Topper
11a12c2c07 [AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead.
The intrinsics will be autoupgraded to the same generic masked loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271478 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-02 04:19:36 +00:00
Rafael Espindola
2f6da59b68 Avoid a load for local functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271437 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 21:57:11 +00:00
Sanjay Patel
7cff23cad5 [x86, AVX2] regenerate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271434 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 21:32:56 +00:00
Michael Kuperstein
d99a2e3ae2 [DAG] Improve legalization of INSERT_SUBVECTOR
When the index is known to be constant 0, insert directly into the the low half,
instead of spilling, performing the insert in-memory, and reloading.

Differential Revision: http://reviews.llvm.org/D20763


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271428 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 20:49:35 +00:00
Keno Fischer
aec5010b27 [PPC64] Fix SUBFC8 Defs list
Fix PR27943 "Bad machine code: Using an undefined physical register".
SUBFC8 implicitly defines the CR0 register, but this was omitted in
the instruction definition.

Patch by Jameson Nash <jameson@juliacomputing.com>

Reviewers: hfinkel
Differential Revision: http://reviews.llvm.org/D20802

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271425 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 20:31:07 +00:00
Than McIntosh
90ac7e3463 Better fix for PR27903.
Summary:
Re-enable lifetime-start-on-first-use for stack coloring,
but explicitly disable it for slots with more than one start
or end lifetime marker.

Bug: 27903

Reviewers: wmi, tejohnson, qcolombet, gbiv

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20739

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271412 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 17:55:10 +00:00
Simon Pilgrim
90828513f4 [X86][SSE] Added non-temporal store tests for all 512-bit vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271393 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 13:58:00 +00:00
Simon Pilgrim
9bc536be82 [X86][SSE] Added non-temporal store tests for all 256-bit vector types
Also added KNL AVX-512 checks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271391 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 13:20:25 +00:00
Simon Pilgrim
b79ae3d5b7 [X86][SSE] Added non-temporal store tests for all 128-bit integer vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271389 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 13:05:00 +00:00
Michael Zuckerman
ac3b4c962d Adding back-end support to two bit scanning intrinsics
Adding LLVM back-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse.
Their functionality is as described in Intel intrinsics guide:
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370

Commit on behalf of Omer Paparo Bivas


Differential Revision: http://reviews.llvm.org/D19915



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271386 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 12:02:37 +00:00
Oliver Stannard
0144de5262 [ARM] Add additional matching for UBFX instructions
This adds an additional matcher to select UBFX(..) from SRL(AND(..)) in
ARMISelDAGToDAG to help with code size.

Patch by David Green.

Differential Revision: http://reviews.llvm.org/D20667



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271384 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 12:01:01 +00:00
Chris Dewhurst
c958a733af [Sparc] Allow passing of empty structs.
Passing an empty struct as a function call argument is now supported.

unit tests for various scenarios added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271374 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 08:48:56 +00:00
Craig Topper
323e9f1870 Revert r271362 "[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead."
Looks like something isn't quite right still. Also forgot to move the test cases to an autoupgrade test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271363 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 05:57:55 +00:00
Craig Topper
c1bee8aab0 [AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead.
The intrinsics will be autoupgraded to the same generic masked loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271362 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-01 05:35:16 +00:00
Matthias Braun
1cd242fe11 CodeGen: Refactor renameDisconnectedComponents() as a pass
Refactor LiveIntervals::renameDisconnectedComponents() to be a pass.
Also change the name to "RenameIndependentSubregs":

- renameDisconnectedComponents() worked on a MachineFunction at a time
  so it is a natural candidate for a machine function pass.

- The algorithm is testable with a .mir test now.

- This also fixes a problem where the lazy renaming as part of the
  MachineScheduler introduced IMPLICIT_DEF instructions after the number
  of a nodes in a region were counted leading to a mismatch.

Differential Revision: http://reviews.llvm.org/D20507

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271345 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 22:38:06 +00:00
Kevin B. Smith
5830c5c818 [X86]: Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live.
Differential Revision: http://reviews.llvm.org/D20649


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271341 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 22:00:12 +00:00
Matthias Braun
b4b32e0649 ARM: Improve/fix comment in recently added test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271340 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 21:59:59 +00:00
Matthias Braun
fe23302cc8 ARM: Do not attempt to modify register class of physregs.
Physregs have no associated register class, do not attempt to modify it
in Thumb2InstrInfo::storeRegToStackSlot()/loadFromStackSlot().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271339 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 21:39:12 +00:00
Ahmed Bougacha
2027459e9a [CodeGen] Promote FMINNAN/FMAXNAN like other binops.
We think it's OK to generate half fminnan because it's legal for the
transform-to type (f32; r245196). However, PromoteFloatRes was missing
the case; simply promote like the other binops, including minnum.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271317 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 18:50:25 +00:00
Rafael Espindola
f2b59e8119 Delete AArch64II::MO_CONSTPOOL.
A constant pool holding the address of a variable in equivalent to
a got entry. It produces exactly the same instruction sequence as a
got use and unlike a got use this is not uniqued by the linker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271311 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 18:31:14 +00:00
Rafael Espindola
1a9c272521 Add a use of shouldAssumeDSOLocal to ARM.
Now this code path knows about position independent executables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271290 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 15:31:55 +00:00
Ranjeet Singh
c146d1a1e5 [ARM] Add backend support for load/store intrinsics.
Added support to map intrinsics
__builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l}
to their ARM instructions.

Differential Revision: http://reviews.llvm.org/D20564



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271271 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 12:39:30 +00:00
Simon Pilgrim
a8a5e74bf9 [X86][SSE] Add load-folding patterns for (V)CVTDQ2PD (PR27291)
Added patterns for (V)CVTDQ2PD -> 2f64 loading from a 64-bit source.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271269 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 12:04:35 +00:00
Simon Dardis
8140f781f2 [mips] bnec/beqc register constraint fix
beqc and bnec cannot have $rs == $rt. Inhibit compact branch creation
if that would occur.

Reviewers: vkalintiris, dsanders

Differential Revision: http://reviews.llvm.org/D20624


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271260 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 09:54:55 +00:00
Igor Breger
ae9c817ebb [AVX512] Fix intrinsic vcvtps2ph lowering.
Differential Revision: http://reviews.llvm.org/D20788

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271255 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 08:04:21 +00:00
Igor Breger
7720e47020 Fix intrinsic vbroadcast{i32|f32}x2 lowering.
Differential Revision: http://reviews.llvm.org/D20780

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271254 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 07:43:39 +00:00
Craig Topper
acc7ed7b83 [AVX512] Remove masked store intrinsics. Clang now emits generic masked store intrinsics instead.
The intrinsics will be autoupgraded to the same generic masked stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271245 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 01:50:02 +00:00
Saleem Abdulrasool
a2bdb6de81 X86: permit using SjLj EH on x86 targets as an option
This adds support to the backed to actually support SjLj EH as an exception
model.  This is *NOT* the default model, and requires explicitly opting into it
from the frontend.  GCC supports this model and for MinGW can still be enabled
via the `--using-sjlj-exceptions` options.

Addresses PR27749!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271244 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-31 01:48:07 +00:00
Craig Topper
2463f3bdaa [X86] Remove SSE/AVX unaligned store intrinsics as clang no longer uses them. Auto upgrade to native unaligned store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271236 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-30 23:15:56 +00:00
Craig Topper
83ed492499 [X86] Use update_llc_test_checks.py to re-generate a test in preparation for an upcoming commit. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271234 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-30 22:54:14 +00:00
Simon Pilgrim
47ca2d83df [X86][XOP] Split off auto-upgraded xop intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271228 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-30 19:50:56 +00:00
Simon Pilgrim
4dedbb6410 [X86][SSE] Renamed pmovxrm tests
These aren't intrinsics anymore - as discussed on D20686

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271226 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-30 19:14:37 +00:00
Simon Pilgrim
16a2da8f0e [X86][AVX2] Regenerated AVX2 extension tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271224 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-30 18:49:57 +00:00
Simon Pilgrim
e03d7f3fb0 [X86][SSE] Updated storeu fast-isel tests to match clang builtin tests
Since rL271214 the headers have no longer used the storeu intrinsic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271222 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-30 18:42:51 +00:00
Simon Pilgrim
5aef47d5b7 [X86][SSE2] Updated _mm_store_pd1/_mm_store1_pd fast-isel tests to match D20617
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271220 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-30 18:18:44 +00:00
Diana Picus
e7cbdab8a9 [BPF] Remove exit-on-error from tests (PR27768, PR27769)
The exit-on-error flag is necessary to avoid some assertions/unreachables. We
can get past them by creating a few dummy nodes.

Fixes PR27768, PR27769.

Differential Revision: http://reviews.llvm.org/D20726

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271200 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-30 08:28:34 +00:00
Simon Pilgrim
687467768e [X86][SSE] (Reapplied) Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm)
This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused.

Reapplied now that the the companion patch (D20684) removes/auto-upgrade the clang intrinsics has been committed.

Differential Revision: http://reviews.llvm.org/D20686

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271131 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-28 18:03:41 +00:00
Sanjay Patel
aea5485cfe [x86] avoid printing unnecessary sign bits of hex immediates in asm comments (PR20347)
It would be better to check the valid/expected size of the immediate operand, but this is
generally better than what we print right now.

Differential Revision: http://reviews.llvm.org/D20385



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271114 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-28 14:58:37 +00:00
Ahmed Bougacha
fe422064d9 [X86] Try to zero elts when lowering 256-bit shuffle with PSHUFB.
Otherwise we fallback to a blend of PSHUFBs later on.

Differential Revision: http://reviews.llvm.org/D19661

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271113 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-28 14:38:04 +00:00
Rafael Espindola
f57428de58 Fix default reloc model on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271111 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-28 10:41:15 +00:00
Renato Golin
b0771c89b2 Revert "Revert "Map DynamicNoPIC to Static on non-darwin.""
This reverts commit r271096, as reverting it broke even more buildbots!

But that also means I'll break on ARM again... :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271099 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-28 04:47:13 +00:00
Renato Golin
ff7695ffc7 Revert "Map DynamicNoPIC to Static on non-darwin."
This reverts commit r271052, as it broke some ARM buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271096 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-28 04:24:26 +00:00
Matt Arsenault
c3eeba0f4c AMDGPU: Cleanup vector insert/extract tests
This mostly makes sure that 3-vector dynamic inserts
and extracts are covered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271082 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-28 00:51:06 +00:00
Matt Arsenault
14cb586d5e AMDGPU: Add fract intrinsic
Remove broken patterns matching it. This was matching the
unsafe math pattern and expanding the fix for the buggy instruction
from the pattern. The problems are also on CI. Remove the workarounds
and only use fract with unsafe math or from the intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271078 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-28 00:19:52 +00:00
Rafael Espindola
a31d45bb57 Map DynamicNoPIC to Static on non-darwin.
DynamicNoPIC was only every used on darwin. This maps it to static on
ELF. It matches what is done on X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271052 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-27 21:44:18 +00:00
Michael Kuperstein
780aab5bdb [X86] Detect SAD patterns and emit psadbw instructions.
This recommits r267649 with a fix for PR27539.

Differential Revision: http://reviews.llvm.org/D20598


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271033 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-27 18:53:22 +00:00