954 Commits

Author SHA1 Message Date
Leonard Chan
8e3fdeb3b8 [Intrinsic] Signed Fixed Point Multiplication Intrinsic
Add an intrinsic that takes 2 signed integers with the scale of them provided
as the third argument and performs fixed point multiplication on them.

This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.

Differential Revision: https://reviews.llvm.org/D54719

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348912 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-12 06:29:14 +00:00
Simon Pilgrim
4653c9ad51 [TargetLowering] Add ISD::EXTRACT_VECTOR_ELT support to SimplifyDemandedBits
Let SimplifyDemandedBits attempt to simplify all elements of a vector extraction.

Part of PR39689.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348839 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-11 11:08:40 +00:00
Simon Pilgrim
db716b5543 [TargetLowering] Add UNDEF folding to SimplifyDemandedVectorElts
If all the demanded elements of the SimplifyDemandedVectorElts are known to be UNDEF, we can simplify to an ISD::UNDEF node.

Zero constant folding will be handled in a future patch - its a little trickier as we often have bitcasted zero values.

Differential Revision: https://reviews.llvm.org/D55511

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348784 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-10 18:29:46 +00:00
Simon Pilgrim
b2a7ed6a26 [TargetLowering] Remove ISD::ANY_EXTEND/ANY_EXTEND_VECTOR_INREG opcodes from SimplifyDemandedVectorElts
These have no test coverage and the KnownZero flags can't be guaranteed unlike SIGN/ZERO_EXTEND cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348361 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-05 12:20:05 +00:00
Simon Pilgrim
67f4757dce [SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467)
This is an initial patch to add a minimum level of support for funnel shifts to the SelectionDAG and to begin wiring it up to the X86 SHLD/SHRD instructions.

Some partial legalization code has been added to handle the case for 'SlowSHLD' where we want to expand instead and I've added a few DAG combines so we don't get regressions from the existing DAG builder expansion code.

Differential Revision: https://reviews.llvm.org/D54698

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348353 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-05 11:12:12 +00:00
Simon Pilgrim
cf6cfbd9bb [TargetLowering] SimplifyDemandedVectorElts - don't alter DemandedElts mask
Fix potential issue with the ISD::INSERT_VECTOR_ELT case tweaking the DemandedElts mask instead of using a local copy - so later uses of the mask use the tweaked version.....

Noticed while investigating adding zero/undef folding to SimplifyDemandedVectorElts and the altered DemandedElts mask was causing mismatches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348348 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-05 10:37:45 +00:00
Nirav Dave
02f12eea5e [SelectionDAG] Redefine isGAPlusOffset in terms of unwrapAddress. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348288 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-04 17:59:43 +00:00
Simon Pilgrim
2f5801a565 [TargetLowering] expandFP_TO_UINT - avoid FPE due to out of range conversion (PR17686)
PR17686 demonstrates that for some targets FP exceptions can fire in cases where the FP_TO_UINT is expanded using a FP_TO_SINT instruction.

The existing code converts both the inrange and outofrange cases using FP_TO_SINT and then selects the result, this patch changes this for 'strict' cases to pre-select the FP_TO_SINT input and the offset adjustment.

The X87 cases don't need the strict flag but generates much nicer code with it....

Differential Revision: https://reviews.llvm.org/D53794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348251 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-04 11:21:30 +00:00
Simon Pilgrim
8254306a0e [TargetLowering] Add SimplifyDemandedVectorElts support to EXTEND opcodes
Add support for ISD::*_EXTEND and ISD::*_EXTEND_VECTOR_INREG opcodes.

The extra broadcast in trunc-subvector.ll will be fixed in an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348246 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-04 10:41:06 +00:00
Simon Pilgrim
b0510431f2 [SelectionDAG] Improve SimplifyDemandedBits to SimplifyDemandedVectorElts simplification
D52935 introduced the ability for SimplifyDemandedBits to call SimplifyDemandedVectorElts through BITCASTs if the demanded bit mask entirely covered the sub element.

This patch relaxes this to demanding an element if we need any bit from it.

Differential Revision: https://reviews.llvm.org/D54761

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348073 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-01 12:08:55 +00:00
Simon Pilgrim
d0658beb2f [TargetLowering] SimplifyDemandedBits - only reduce known bits for integer constants
Avoids fuzzing crash found by Mikael Holmén.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347393 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-21 14:26:19 +00:00
Simon Pilgrim
f1f291e60c [DAGCombine] Add calls to SimplifyDemandedVectorElts from visitINSERT_SUBVECTOR (PR37989)
This uncovered an off-by-one typo in SimplifyDemandedVectorElts's INSERT_SUBVECTOR handling as its bounds check was bailing on safe indices.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347313 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-20 15:23:50 +00:00
Simon Pilgrim
8f862e5873 [TargetLowering] Improve SimplifyDemandedVectorElts/SimplifyDemandedBits support
For bitcast nodes from larger element types, add the ability for SimplifyDemandedVectorElts to call SimplifyDemandedBits by merging the elts mask to a bits mask.

I've raised https://bugs.llvm.org/show_bug.cgi?id=39689 to deal with the few places where SimplifyDemandedBits's lack of vector handling is a problem.

Differential Revision: https://reviews.llvm.org/D54679

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347301 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-20 12:02:16 +00:00
Simon Pilgrim
ab88d0c40f [TargetLowering] expandFP_TO_UINT - improve fp16 support
As discussed on D53794, for float types with ranges smaller than the destination integer type, then we should be able to just use a regular FP_TO_SINT opcode.

I thought we'd need to provide MSA test cases for very small integer types as well (fp16 -> i8 etc.), but it turns out that promotion will kick in so they're unnecessary.

Differential Revision: https://reviews.llvm.org/D54703

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347251 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-19 19:16:13 +00:00
Simon Pilgrim
0478924a37 [TargetLowering] Cleanup more of the EXTEND demanded bits cases so that they match. NFCI.
Use the same variable names etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347045 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-16 12:26:26 +00:00
Simon Pilgrim
e3b515280e [TargetLowering] Begin generalizing TargetLowering::expandFP_TO_SINT support. NFCI.
Prior to initial work to add vector expansion support, remove assumptions that we're working on scalar types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346139 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-05 15:49:09 +00:00
Simon Pilgrim
03e8599949 [LegalizeDAG] Add generic vector CTPOP expansion (PR32655)
This patch adds support for expanding vector CTPOP instructions and removes the x86 'bitmath' lowering which replicates the same expansion.

Differential Revision: https://reviews.llvm.org/D53258

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345869 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-01 18:22:11 +00:00
Stanislav Mekhanoshin
832efd7ec3 Check shouldReduceLoadWidth from SimplifySetCC
SimplifySetCC could shrink a load without checking for
profitability or legality of such shink with a target.

Added checks to prevent shrinking of aligned scalar loads
in AMDGPU below dword as scalar engine does not support it.

Differential Revision: https://reviews.llvm.org/D53846

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345778 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-31 21:24:30 +00:00
Leonard Chan
5aeb36fdcb [Intrinsic] Signed and Unsigned Saturation Subtraction Intirnsics
Add an intrinsic that takes 2 integers and perform saturation subtraction on
them.

This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.

Differential Revision: https://reviews.llvm.org/D53783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345512 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-29 16:54:37 +00:00
Simon Pilgrim
1798150a2b [TargetLowering] Move i64/vXi64 to f32/vXf32 UINT_TO_FP handling to TargetLowering::expandUINT_TO_FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345478 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-28 15:34:35 +00:00
Simon Pilgrim
5c0be92e19 [VectorLegalizer] Enable TargetLowering::expandFP_TO_UINT support.
Add vector support to TargetLowering::expandFP_TO_UINT.

This exposes an issue in X86TargetLowering::LowerVSELECT which was assuming that the select mask was the same width as the LHS/RHS ops - as long as the result is a sign splat we can easily sext/trunk this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345473 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-28 13:07:25 +00:00
Simon Pilgrim
57aa4fc38b [TargetLowering] Move LegalizeDAG FP_TO_UINT handling to TargetLowering::expandFP_TO_UINT. NFCI.
First step towards fixing PR17686 and adding vector support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345452 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-27 12:15:58 +00:00
Simon Pilgrim
f86533efab [TargetLowering] Improve vXi64 UINT_TO_FP vXf64 support (P38226)
As suggested on D52965, this patch moves the i64 to f64 UINT_TO_FP expansion code from LegalizeDAG into TargetLowering and makes it available to LegalizeVectorOps as well.

Not only does this help perform X86 lowering as a true vectorization instead of (partially vectorized) scalar conversions, it avoids the HADDPD op from the scalar code which can be slow on most targets.

The AVX512F does have the vcvtusi2sdq scalar operation but we don't unroll to use it as it seems to only help for the v2f64 case - otherwise the unrolling cost will certainly be too high. My feeling is that we should leave it to the vectorizers - and if it generates the vector UINT_TO_FP we should use it.

Differential Revision: https://reviews.llvm.org/D53649


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345256 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-25 11:15:57 +00:00
Simon Pilgrim
3cc8b4921a [TargetLowering] Add SimplifyDemandedBitsForTargetNode callback
Add a SimplifyDemandedBitsForTargetNode callback to handle target nodes.

Differential Revision: https://reviews.llvm.org/D53643

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345179 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-24 19:00:56 +00:00
Simon Pilgrim
d537407cfe [LegalizeDAG] Share Vector/Scalar CTPOP Expansion
As suggested on D53258, this patch move the CTPOP expansion code from SelectionDAGLegalize to TargetLowering to allow it to be reused by the VectorLegalizer.

Proper vector support will be added by D53258.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345066 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-23 18:28:24 +00:00
Simon Pilgrim
79b7ee9344 [LegalizeDAG] Share Vector/Scalar CTLZ Expansion
As suggested on D53258, this patch shares common CTLZ expansion code between VectorLegalizer and SelectionDAGLegalize by putting it in TargetLowering.

Extension to D53474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345060 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-23 17:48:30 +00:00
Simon Pilgrim
e3237d202f [LegalizeDAG] Share Vector/Scalar CTTZ Expansion
As suggested on D53258, this patch demonstrates sharing common CTTZ expansion code between VectorLegalizer and SelectionDAGLegalize by putting it in TargetLowering.

I intend to move CTLZ and (scalar) CTPOP over as well and then update D53258 accordingly.

Differential Revision: https://reviews.llvm.org/D53474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345039 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-23 15:37:19 +00:00
Leonard Chan
152aae5d0d [Intrinsic] Unigned Saturation Addition Intrinsic
Add an intrinsic that takes 2 integers and perform unsigned saturation
addition on them.

This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.

Differential Revision: https://reviews.llvm.org/D53340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344971 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-22 23:08:40 +00:00
Matt Arsenault
c0db9a7416 DAG: Change behavior of fminnum/fmaxnum nodes
Introduce new versions that follow the IEEE semantics
to help with legalization that may need quieted inputs.

There are some regressions from inserting unnecessary
canonicalizes when these are matched from fast math
fcmp + select which should be fixed in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344914 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-22 16:27:27 +00:00
Leonard Chan
b325eb110c [Intrinsic] Signed Saturation Addition Intrinsic
Add an intrinsic that takes 2 integers and perform saturation addition on them.

This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.

Differential Revision: https://reviews.llvm.org/D53053

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344629 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-16 17:35:41 +00:00
Sanjay Patel
abfefc95ba [SelectionDAG] allow FP binops in SimplifyDemandedVectorElts
This is intended to make the backend on par with functionality that was 
added to the IR version of SimplifyDemandedVectorElts in:
rL343727
...and the original motivation is that we need to improve demanded-vector-elements 
in several ways to avoid problems that would be exposed in D51553.

Differential Revision: https://reviews.llvm.org/D52912


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344541 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-15 18:05:34 +00:00
Simon Pilgrim
efbdbcea74 [TargetLowering] SimplifyDemandedBits - rename demanded mask args. NFCI.
Help stop bugs like rL343935 by making the 'original' DemandedBits arg more obviously not the mask that is actually used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344138 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-10 13:00:49 +00:00
Simon Pilgrim
c195d382a1 [TargetLowering] SimplifyDemandedBits - pull out repeated getOperands. NFCI.
Part of a minor cleanup to make all the switch statements more consistent prior to improving vector support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344136 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-10 12:32:13 +00:00
Simon Pilgrim
f9d46e9db3 [TargetLowering] Add root node back to work list after successful SimplifyDemandedBits/SimplifyDemandedVectorElts
Similar to what already happens in the DAGCombiner wrappers, this patch adds the root nodes back onto the worklist if the DCI wrappers' SimplifyDemandedBits/SimplifyDemandedVectorElts were successful.

Differential Revision: https://reviews.llvm.org/D53026

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344132 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-10 10:44:15 +00:00
Simon Pilgrim
e574f76b8f [SelectionDAG] Add SIGN_EXTEND_VECTOR_INREG and CONCAT_VECTORS support to SimplifyDemandedBits
Fix for AVX1 masked load/store regression on D52964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344043 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-09 13:13:35 +00:00
Simon Pilgrim
b1a2f9aee3 [SelectionDAG] Respect multiple uses in SimplifyDemandedBits to SimplifyDemandedVectorElts simplification
rL343913 was using SimplifyDemandedBits's original demanded mask instead of the adjusted 'NewMask' that accounts for multiple uses of the op (those variable names really need improving....).

Annoyingly many of the test changes (back to pre-rL343913 state) are actually safe - but only because their multiple uses are all by PMULDQ/PMULUDQ.

Thanks to Jan Vesely (@jvesely) for bisecting the bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343935 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-07 11:45:46 +00:00
Simon Pilgrim
0d0e510068 [SelectionDAG] Add SimplifyDemandedBits to SimplifyDemandedVectorElts simplification
This patch enables SimplifyDemandedBits to call SimplifyDemandedVectorElts in cases where the demanded bits mask covers entire elements of a bitcasted source vector.

There are a couple of cases here where simplification at a deeper level (such as through bitcasts) prevents further simplification - CommitTargetLoweringOpt only adds immediate uses/users back to the worklist when we might want to combine the original caller again to see what else it can simplify.

As well as that I had to disable handling of bool vector until SimplifyDemandedVectorElts better supports some of their opcodes (SETCC, shifts etc.).

Fixes PR39178

Differential Revision: https://reviews.llvm.org/D52935

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343913 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-06 10:20:04 +00:00
David Green
ae073c99a4 [CodeGen] Enable tail calls for functions with NonNull attributes.
Adding NonNull as attributes to returned pointers has the unfortunate side
effect of disabling tail calls. This patch ignores the NonNull attribute when
we decide whether to tail merge, in the same way that we ignore the NoAlias
attribute, as it has no affect on the call sequence.

Differential Revision: https://reviews.llvm.org/D52238


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343091 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 10:46:18 +00:00
Matt Arsenault
21339d63b9 DAG: Fix expansion of unaligned FP loads and stores
This was trying to scalarizing a scalar FP type,
resulting in an assert.

Fixes unaligned f64 stack stores for AMDGPU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342132 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-13 12:14:23 +00:00
Sanjay Patel
250785bc7b [SelectionDAG] enhance vector demanded elements to look at a vector select condition operand
This is the DAG equivalent of D51433.
If we know we're not using all vector lanes, use that knowledge to potentially simplify a vselect condition.

The reduction/horizontal tests show that we are eliminating AVX1 operations on the upper half of 256-bit 
vectors because we don't need those anyway.
I'm not sure what the pr34592 test is showing. That's run with -O0; is SimplifyDemandedVectorElts supposed 
to be running there?

Differential Revision: https://reviews.llvm.org/D51696


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341762 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-09 14:13:22 +00:00
Scott Linder
c7d9aac718 [CodeGen] Fix remaining zext() assertions in SelectionDAG
Fix remaining cases not committed in https://reviews.llvm.org/D49574

Differential Revision: https://reviews.llvm.org/D50659


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341380 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-04 16:33:34 +00:00
Roman Lebedev
41b17bcd0d [DAGCombine] optimizeSetCCOfSignedTruncationCheck(): handle inverted pattern
Summary:
A follow-up for D49266 / rL337166 + D49497 / rL338044.

This is still the same pattern to check for the [lack of]
signed truncation, but in this case the constants and the predicate
are negated.

https://rise4fun.com/Alive/BDV
https://rise4fun.com/Alive/n7Z

Reviewers: spatel, craig.topper, RKSimon, javed.absar, efriedma, dmgreen

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D51532

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341287 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-02 13:56:22 +00:00
Simon Pilgrim
d92e522f12 [TargetLowering] Add BuildSDiv support for division by one or negone.
This reduces most of the sdiv stages (the MULHS, shifts etc.) to just zero/identity values and use the numerator scale factor to multiply by +1/-1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340260 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-21 10:20:36 +00:00
Simon Pilgrim
f1f733e717 [TargetLowering] Disable BuildSDiv division by one or negone.
Fuzz tests have detected an issue, currently working on a fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340195 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-20 18:23:54 +00:00
Simon Pilgrim
465c62b8d3 [TargetLowering] Add support for non-uniform vectors to BuildSDIV
This patch refactors the existing TargetLowering::BuildSDIV base implementation to support non-uniform constant vector denominators.

This is the last patch necessary to close PR36545

Differential Revision: https://reviews.llvm.org/D50765

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339908 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-16 17:44:33 +00:00
Simon Pilgrim
3b2cfd19a0 [TargetLowering] Refactor BuildSDIV in preparation for D50765. NFCI.
Pull out magic factor calculators into a helper function, use 0/+1/-1 multiplication factor to (optionally) add/sub the numerator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339898 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-16 16:54:06 +00:00
Matt Arsenault
982d395b2a DAG: Use getObjectOffset helper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339813 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-15 21:03:44 +00:00
Simon Pilgrim
f965428b0e [TargetLowering] Minor cleanup of TargetLowering::BuildSDIV. NFCI.
Pull out some types to match layout in TargetLowering::BuildUDIV. Early step towards adding non-uniform vector support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339763 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-15 11:11:05 +00:00
Simon Pilgrim
0f7eb9f532 [TargetLowering] Minor refactor to TargetLowering::BuildUDIV to merge scalar/vector magic value collection. NFCI.
Use the same ISD::matchUnaryPredicate pattern that was used in D50392.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339758 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-15 10:11:13 +00:00
Simon Pilgrim
7e6dd0cff7 [TargetLowering] Add support for non-uniform vectors to BuildExactSDIV
This patch refactors the existing BuildExactSDIV implementation to support non-uniform constant vector denominators.

Differential Revision: https://reviews.llvm.org/D50392

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339756 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-15 09:35:12 +00:00