Commit Graph

142597 Commits

Author SHA1 Message Date
Petar Jovanovic
71e6bc584f [mips] Fix compact branch hazard detection, part 2
Follow up to D27209 fix, this patch now properly handles single transient
instruction in basic block.

Patch by Aleksandar Beserminji.

Differential Revision: https://reviews.llvm.org/D27856


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290361 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 19:29:50 +00:00
Krzysztof Parzyszek
8bfcb04e0e Add the DAG mutation interface to the software pipeliner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290360 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 19:21:20 +00:00
Reid Kleckner
e1c9f504c6 Pass -Wa,-mbig-obj in 64-bit mingw builds
COFF has a 2**16 section limit, and on Win64, every COMDAT function
creates at least 3 sections: .text, .pdata, and .xdata. For MSVC, we
enable bigobj on a file-by-file basis, but GCC appears to hit the limit
on different files.

Fixes PR25953

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290358 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 19:12:14 +00:00
Reid Kleckner
1d481d5a86 Build KillTheDoctor with mingw-w64
compiler-rt uses it in its lit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290357 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 19:11:42 +00:00
Krzysztof Parzyszek
2272dc886c Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
When the pipeliner is renaming phi values, it may need to iterate through
the phi operands to check for other phis. However, the pipeliner should
stop once it reaches a phi that is outside the pipelined loop.

Also, when the generateExistingPhis code is unable to reuse an existing
phi, the default code that computes the PhiOp2 is only to be used when
the pipeliner is generating the kernel. Otherwise, the phi may be a value
computed earlier in the same epilog.

Patch by Brendon Cahoon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290355 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 18:49:55 +00:00
Matt Arsenault
ad47821c65 AMDGPU: Use i16 for i16 shift amount
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290351 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 16:36:25 +00:00
Davide Italiano
ee1439d664 [NewGVN] Add the pass to PassRegistry.def.
We need to hook up here to get it working with the new PM.
Add a test while here (and remove a typo).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290350 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 16:35:02 +00:00
Matt Arsenault
b1e16f2d3a AMDGPU: Fix missing 16-bit cmpx instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290349 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 16:27:14 +00:00
Matt Arsenault
8d973070a0 AMDGPU: Use i16 comparison instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290348 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 16:27:11 +00:00
Matt Arsenault
61ec8435ca AMDGPU: Fixed '!NodePtr->isKnownSentinel()' assert
Caused by dereferencing end iterator when trying to const cast the iterator.

Patch by Martin Sherburn

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290347 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 16:06:32 +00:00
Davide Italiano
65696f40e4 [GVN] Initial check-in of a new global value numbering algorithm.
The code have been developed by Daniel Berlin over the years, and
the new implementation goal is that of addressing shortcomings of
the current GVN infrastructure, i.e. long compile time for large
testcases, lack of phi predication, no load/store value numbering
etc...

The current code just implements the "core" GVN algorithm, although
other pieces (load coercion, phi handling, predicate system) are
already implemented in a branch out of tree. Once the core is stable,
we'll start adding pieces on top of the base framework.
The test currently living in test/Transform/NewGVN are a copy
of the ones in GVN, with proper `XFAIL` (missing features in NewGVN).
A flag will be added in a future commit to enable NewGVN, so that
interested parties can exercise this code easily.

Differential Revision:  https://reviews.llvm.org/D26224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290346 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 16:03:48 +00:00
Dan Gohman
474281748f [WebAssembly] Add an "explicit" keyword to a constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290345 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 16:03:02 +00:00
Dan Gohman
eb97b39da3 [WebAssembly] Don't use variadic operand indices in the MCOperandInfo array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290344 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 16:00:55 +00:00
Dan Gohman
9c0b078bc0 [WebAssembly] Don't old negative load/store offsets in fast-isel.
WebAssembly's load/store offsets are unsigned and don't wrap, so it's not
valid to fold in a negative offset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290342 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 15:15:10 +00:00
Sam Kolton
7448b08bb6 [AMDGPU] Add pseudo SDWA instructions
Summary: This is needed for later SDWA support in CodeGen.

Reviewers: vpykhtin, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D27412

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290338 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 12:57:41 +00:00
Sam Kolton
b94ac0f1d9 [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa
Summary: Real instruction should copy constraints from real instruction. This allows auto-generated disassembler to correctly process tied operands.

Reviewers: nhaustov, vpykhtin, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D27847

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290336 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 11:30:48 +00:00
Ayman Musa
64a0af2928 [X86][AVX2] Passing the appropriate memory operand class to VPMADDWD instruction.
Replacing the memory operand in the ymm version of VPMADDWD from i128mem to i256mem.

Differential Revision: https://reviews.llvm.org/D28024



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290333 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 08:42:46 +00:00
Chandler Carruth
4bc31e9601 [PM] Loosen the check ever so slightly -- MSVC appears to not include
a space after the comma in template arguments with our hacky type name
system.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290331 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 07:53:20 +00:00
Chandler Carruth
95a32c889c [PM] Make a couple of CHECK lines a bit more precise, NFC.
I was staring at these and didn't realize these were module-layer
proxies as opposed to some other layer. Justin and I have a plan to
rename things to make the names themselves much easier to reason about,
but I at least want the CHECK lines to be precise for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290328 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 07:14:35 +00:00
Chandler Carruth
4ed09f06aa [PM] Remove now-dead extern template and explicit instantiation
declarations.

We're using a custom class here instead of the helper template, these
bits just didn't get deleted when the other bits did get deleted. This
was found by a really nice MSVC warning about explicitly instantiating
a template where some member functions aren't defined and thus can't be
instantiatied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290327 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 07:14:33 +00:00
Chandler Carruth
2ffea51042 [PM] Introduce a reasonable port of the main per-module pass pipeline
from the old pass manager in the new one.

I'm not trying to support (initially) the numerous options that are
currently available to customize the pass pipeline. If we end up really
wanting them, we can add them later, but I suspect many are no longer
interesting. The simplicity of omitting them will help a lot as we sort
out what the pipeline should look like in the new PM.

I've also documented to the best of my ability *why* each pass or group
of passes is used so that reading the pipeline is more helpful. In many
cases I think we have some questionable choices of ordering and I've
left FIXME comments in place so we know what to come back and revisit
going forward. But for now, I've left it as similar to the current
pipeline as I could.

Lastly, I've had to comment out several places where passes are not
ported to the new pass manager or where the loop pass infrastructure is
not yet ready. I did at least fix a few bugs in the loop pass
infrastructure uncovered by running the full pipeline, but I didn't want
to go too far in this patch -- I'll come back and re-enable these as the
infrastructure comes online. But I'd like to keep the comments in place
because I don't want to lose track of which passes need to be enabled
and where they go.

One thing that seemed like a significant API improvement was to require
that we don't build pipelines for O0. It seems to have no real benefit.

I've also switched back to returning pass managers by value as at this
API layer it feels much more natural to me for composition. But if
others disagree, I'm happy to go back to an output parameter.

I'm not 100% happy with the testing strategy currently, but it seems at
least OK. I may come back and try to refactor or otherwise improve this
in subsequent patches but I wanted to at least get a good starting point
in place.

Differential Revision: https://reviews.llvm.org/D28042

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290325 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 06:59:15 +00:00
Adrian Prantl
fddea6af8d Fix an assertion in DwarfExpression when emitting fragments in vector registers
When DwarfExpression is emitting a fragment that is located in a
register and that fragment is smaller than the register, and the
register must be composed from sub-registers (are you still with me?)
the last DW_OP_piece operation must not be larger than the size of the
fragment itself, since the last piece of the fragment could be smaller
than the last subregister that is being emitted.

rdar://problem/29779065

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290324 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 06:10:41 +00:00
Adrian Prantl
f53a7ab5bb Refactor the DIExpression fragment query interface (NFC)
... so it becomes available to DIExpressionCursor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290322 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 05:27:12 +00:00
Matt Arsenault
27bb0f08ca DAG: Add helper for testing constant values
There are helpers for testing for constant or constant build_vector,
and for splat ConstantFP vectors, but not for a constantfp or
non-splat ConstantFP vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290317 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 04:39:45 +00:00
Matt Arsenault
1f1e46113e AMDGPU: Fix missing commute table entries for cmpx
No tests because these aren't currently used anywhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290316 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 04:39:41 +00:00
Mehdi Amini
b78d89e96e [ThinLTO] Save 8B per summary entry by rearranging the fields (NFC)
Size goes from 72B to 64B per entry.

Differential Revision: https://reviews.llvm.org/D27970

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290314 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 04:09:29 +00:00
Matt Arsenault
46e5f1c88d AMDGPU: Swap order of operands in fadd/fsub combine
FMA is canonicalized to constant in the middle operand. Do
the same so fmad matches and avoid an extra combine step.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290313 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 04:03:40 +00:00
Matt Arsenault
121f8654d3 AMDGPU: Check fast math flags in fadd/fsub combines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290312 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 04:03:35 +00:00
Matt Arsenault
ff4096b8f8 AMDGPU: Form more FMAs if fusion is allowed
Extend the existing fadd/fsub->fmad combines to produce
FMA if allowed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290311 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:55:35 +00:00
Matt Arsenault
121cd504bf AMDGPU: Move combines into separate functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290309 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:44:42 +00:00
Matt Arsenault
75c32f5150 AMDGPU: Enable some f32 fadd/fsub combines for f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290308 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:40:39 +00:00
Matt Arsenault
cee1c4614a AMDGPU: Implement isFMAFasterThanFMulAndFAdd for f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290307 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:21:48 +00:00
Matt Arsenault
998b18c570 AMDGPU: setcc test cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290306 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:21:45 +00:00
Matt Arsenault
a8dff18ebc AMDGPU: Allow rcp and rsq usage with f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290302 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:05:44 +00:00
Matt Arsenault
4bb99910b0 AMDGPU: Custom lower f16 fdiv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290301 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:05:41 +00:00
Matt Arsenault
0bb2ef4a14 AMDGPU: Implement f16 fcanonicalize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290300 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:05:37 +00:00
Matt Arsenault
15a4f4e4ce AMDGPU: Update isFPImmLegal for f16
I don't think this matters because ConstantFP is legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290299 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 03:05:30 +00:00
Peter Collingbourne
50b4952766 Clear the PendingTypeTests vector after moving from it.
This is to put the vector into a well defined state. Apparently the state of a
vector after being moved from is valid but unspecified. Found with clang-tidy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290298 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 02:52:23 +00:00
Haicheng Wu
48addbf5f8 [AArch64] Correct the check of signed 9-bit imm in getIndexedAddressParts().
-256 is a legal indexed address part.

Differential Revision: https://reviews.llvm.org/D27537

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290296 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 01:39:24 +00:00
Easwaran Raman
94201fb8e7 Pass GetAssumptionCache to InlineFunctionInfo constructor
Differential revision: https://reviews.llvm.org/D28038


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290295 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 01:07:01 +00:00
David Majnemer
f35020be62 [NVVMIntrRange] Only set range metadata if none is already present
The range metadata inserted by NVVMIntrRange is pessimistic, range
metadata already present could be more precise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290294 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 00:51:59 +00:00
Adrian Prantl
c271bc0481 Renumber testcase metadata nodes after r290153.
This patch renumbers the metadata nodes in debug info testcases after
https://reviews.llvm.org/D26769. This is a separate patch because it
causes so much churn. This was implemented with a python script that
pipes the testcases through llvm-as - | llvm-dis - and then goes
through the original and new output side-by side to insert all
comments at a close-enough location.

Differential Revision: https://reviews.llvm.org/D27765

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290292 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 00:45:21 +00:00
Adrian Prantl
ee92d2e1b2 [LLParser] Make the line field of DIMacro(File) optional.
Otherwise these records do not survive roundtrips.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290291 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22 00:29:00 +00:00
Adrian Prantl
5cfe3c370f Legalize metadata in legacy testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290288 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 23:38:17 +00:00
Adrian Prantl
7d9914dcc1 Legalize metadata in legacy testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290287 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 23:36:06 +00:00
Adrian Prantl
0f7c9fbaa2 Legalize metadata in legacy testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290286 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 23:30:35 +00:00
Adrian Prantl
6b556068df Legalize metadata in legacy testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290285 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 23:28:49 +00:00
Ahmed Bougacha
8097fcb40b [GlobalISel] Add basic Selector-emitter tblgen backend.
This adds a basic tablegen backend that analyzes the SelectionDAG
patterns to find simple ones that are eligible for GlobalISel-emission.

That's similar to FastISel, with one notable difference: we're not fed
ISD opcodes, so we need to map the SDNode operators to generic opcodes.
That's done using GINodeEquiv in TargetGlobalISel.td.

Otherwise, this is mostly boilerplate, and lots of filtering of any kind
of "complicated" pattern. On AArch64, this is sufficient to match G_ADD
up to s64 (to ADDWrr/ADDXrr) and G_BR (to B).

Differential Revision: https://reviews.llvm.org/D26878

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290284 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 23:26:20 +00:00
Ahmed Bougacha
9cccec8198 [AsmWriter] Remove redundant cast<>s. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290283 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 23:26:13 +00:00
Dan Gohman
54f9742d29 [WebAssembly] Fix the opcode value for i64.rotr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290281 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 23:09:42 +00:00