2 Commits

Author	SHA1	Message	Date
Matt Arsenault	5d4101dba4	AMDGPU: Handle partial shift reduction for variable shifts ... If the variable shift amount has known bits, we can still reduce the shift. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331917 91177308-0d34-0410-b5e6-96231b3b80d8	2018-05-09 20:52:54 +00:00
Matt Arsenault	c7ccc04824	AMDGPU: Partially shrink 64-bit shifts if reduced to 16-bit ... This is an extension of an existing combine to reduce wider shls if the result fits in the final result type. This introduces the same combine, but reduces the shift to a middle sized type to avoid the slow 64-bit shift. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331916 91177308-0d34-0410-b5e6-96231b3b80d8	2018-05-09 20:52:43 +00:00