 Daniel Sanders
|
09c7f4026a
|
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193239 91177308-0d34-0410-b5e6-96231b3b80d8
|
2013-10-23 10:36:52 +00:00 |
|
|
Daniel Sanders
|
4fa2c32220
|
[mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
|
2013-10-11 10:27:32 +00:00 |
|
|
Daniel Sanders
|
c879eabcc2
|
[mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
|
2013-10-11 10:14:25 +00:00 |
|
|
Daniel Sanders
|
b9bee10b21
|
[mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
|
2013-10-11 10:00:06 +00:00 |
|
|
Daniel Sanders
|
f1ef27e6e3
|
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
|
2013-09-27 10:08:31 +00:00 |
|
|
Daniel Sanders
|
421dcc5921
|
[mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics)
This covers the case where fmax_a can be used to implement ISD::FABS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191296 91177308-0d34-0410-b5e6-96231b3b80d8
|
2013-09-24 13:02:08 +00:00 |
|
|
Daniel Sanders
|
aa2a162eae
|
[mips][msa] Added test cases that were supposed to be part of r190507, r190509, r190512, and r190518.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190522 91177308-0d34-0410-b5e6-96231b3b80d8
|
2013-09-11 12:39:25 +00:00 |
|