4562 Commits

Author SHA1 Message Date
Sanjay Patel
04827a7eed [x86] improve comments for SHRUNKBLEND node creation; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294344 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:54:16 +00:00
Sanjay Patel
27341a9e0b [x86] use range-for loops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294337 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:18:25 +00:00
Sanjay Patel
6271cac448 [x86] use getSignBit() for clarity; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294333 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:01:35 +00:00
Simon Pilgrim
cab8418968 [X86][SSE] Ensure that vector shift-by-immediate inputs are correctly bitcast to the result type
vXi8/vXi64 vector shifts are often shifted as vYi16/vYi32 types but we weren't always remembering to bitcast the input.

Tested with a new assert as we don't currently manipulate these shifts enough for test cases to catch them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294308 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 14:22:25 +00:00
Simon Pilgrim
0aca40051b [X86][SSE] Combine shuffle nodes with multiple uses if all the users are being combined.
Currently we only combine shuffle nodes if they have a single user to prevent us from causing code bloat by splitting the shuffles into several different combines.

We don't take into account that in some cases we will already have combined all the users during recursively calling up the shuffle tree.

This patch keeps a list of all the shuffle nodes that have been combined so far and permits combining of further shuffle nodes if all its users are in that list.

Differential Revision: https://reviews.llvm.org/D29399

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294183 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-06 13:44:45 +00:00
Simon Pilgrim
0f1d173892 [X86][SSE] Replace insert_vector_elt(vec, -1, idx) with shuffle
Similar to what we already do for zero elt insertion, we can quickly rematerialize 'allbits' vectors so to avoid a unnecessary gpr value and insertion into a vector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294162 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-05 22:50:29 +00:00
Craig Topper
53eca87929 [X86] In LowerTRUNCATE, create an ISD::VECTOR_SHUFFLE instead of explicitly creating a PSHUFB. This will be lowered by regular shuffle lowering to a PSHUFB later.
Similar was already done for several other shuffles in this function.

The test changes are because the old code used explicity zeroing for elements that could have been undef.

While I was here I also changed other shuffle vectors in the same function to use the same input twice instead of creating UNDEF nodes. getVectorShuffle can create the UNDEF for us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294130 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-05 18:33:14 +00:00
Craig Topper
1cfb6c6e52 [X86] Add support for folding (insert_subvector vec1, (extract_subvector vec2, idx1), idx1) -> (blendi vec2, vec1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294112 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-04 23:26:46 +00:00
Craig Topper
7a4069d5de [X86] Simplify the code that turns INSERT_SUBVECTOR into BLENDI. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294111 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-04 23:26:42 +00:00
Simon Pilgrim
da9f518360 [X86][SSE] Add support for combining scalar_to_vector(extract_vector_elt) into a target shuffle.
Correctly flagging upper elements as undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294020 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-03 17:59:58 +00:00
Craig Topper
009a7ee816 [X86] Mark 256-bit and 512-bit INSERT_SUBVECTOR operations as legal and remove the custom lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293969 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-03 00:24:49 +00:00
Reid Kleckner
40a18171ba [X86] Avoid sorted order check in release builds
Effectively reverts r290248 and fixes the unused function warning with
ifndef NDEBUG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293945 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-02 22:06:30 +00:00
Craig Topper
5b6f1112aa [X86] Move turning 256-bit INSERT_SUBVECTORS into BLENDI from legalize to DAG combine.
On one test this seems to have given more chance for DAG combine to do other INSERT_SUBVECTOR/EXTRACT_SUBVECTOR combines before the BLENDI was created. Looks like we can still improve more by teaching DAG combine to optimize INSERT_SUBVECTOR/EXTRACT_SUBVECTOR with BLENDI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293944 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-02 22:02:57 +00:00
Simon Pilgrim
178f518f3e [X86][SSE] Use MOVMSK for all_of/any_of reduction patterns
This is a first attempt at using the MOVMSK instructions to replace all_of/any_of reduction patterns (i.e. an and/or + shuffle chain).

So far this only matches patterns where we are reducing an all/none bits source vector (i.e. a comparison result) but we should be able to expand on this in conjunction with improvements to 'bool vector' handling both in the x86 backend as well as the vectorizers etc.

Differential Revision: https://reviews.llvm.org/D28810

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293880 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-02 11:52:33 +00:00
Craig Topper
502509df25 [X86] Remove some unused DAGCombinerInfo parameters. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293873 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-02 08:03:23 +00:00
Craig Topper
a0d05ab6f4 [X86] Move some INSERT_SUBVECTOR optimizations from legalize to DAG combine.
This moves creation of SUBV_BROADCAST and merging of adjacent loads that are being inserted together.

This is a step towards removing legalizing of INSERT_SUBVECTOR except for vXi1 cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293872 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-02 08:03:20 +00:00
Simon Pilgrim
299e3e8880 [X86][SSE] Remove unused argument. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293777 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-01 16:34:50 +00:00
Simon Pilgrim
30afc90a60 [X86][SSE] Merge SSE2 PINSRW lowering with SSE41 PINSRB/PINSRW lowering. NFCI.
These are identical apart from the extra SSE41 guard for PINSRB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293766 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-01 13:32:19 +00:00
Simon Pilgrim
2563d410c9 [X86][SSE] Add support for combining PINSRB into a target shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293637 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 14:59:44 +00:00
Benjamin Kramer
3bfb126ba5 [X86] Silence unused variable warning in Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293631 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 14:13:53 +00:00
Simon Pilgrim
438897d8de [X86][SSE] Detect unary PBLEND shuffles.
These can appear during shuffle combining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293628 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 13:58:01 +00:00
Simon Pilgrim
e8b7298325 [X86][SSE] Add support for combining PINSRW into a target shuffle.
Also add the ability to recognise PINSR(Vex, 0, Idx).

Targets shuffle combines won't replace multiple insertions with a bit mask until a depth of 3 or more, so we avoid codesize bloat.

The unnecessary vpblendw in clearupper8xi16a will be fixed in an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293627 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 13:51:10 +00:00
Craig Topper
e45c0bf83f [X86] Remove 'else' after 'return'. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293589 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-31 02:09:46 +00:00
Simon Pilgrim
ab1d988959 [X86][SSE] Fix unsigned <= 0 warning in assert. NFCI.
Thanks to @mkuper

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293561 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-30 22:58:44 +00:00
Simon Pilgrim
1380699fd1 [X86][SSE] Generalize the number of decoded shuffle inputs. NFCI.
combineX86ShufflesRecursively can still only handle a maximum of 2 shuffle inputs but everything before it now supports any number of shuffle inputs.

This will be necessary for combining OR(SHUFFLE, SHUFFLE) patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293560 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-30 22:48:49 +00:00
Simon Pilgrim
549b31f040 [X86][SSE] Add support for combining PINSRW+ASSERTZEXT+PEXTRW patterns with target shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293500 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-30 16:58:34 +00:00
Asaf Badouh
3191d3a9f5 [X86][MCU] Minor bug fix for r293469 + test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293478 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-30 13:14:37 +00:00
Asaf Badouh
bd71534b8a [X86][MCU] replace select with bit manipulation instead of branches
Differential Revision: https://reviews.llvm.org/D28354


 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293469 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-30 08:16:59 +00:00
Craig Topper
5a5e8a7eb6 [AVX-512] Don't reuse VSHLI/VSRLI for mask register shifts. VSHLI/VSHRI shift within elements while KSHIFT moves whole elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293448 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-30 00:06:01 +00:00
Craig Topper
ff2c48dbb6 [AVX-512] Fix lowering for mask register concatenation with undef in the lower half.
Previously this test case fired an assertion in getNode because we tried to create an insert_subvector with both input types the same size and the index pointing to half the vector width.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293446 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-29 22:53:33 +00:00
Simon Pilgrim
12186ce14d [X86][SSE] Lower scalar_to_vector(0) to zero vector
Replaces an xor+movd/movq with an xorps which will be shorter in codesize, avoid an int-fpu transfer, allow modern cores to fast path the result during decode and helps other combines recognise an all-zero vector.

The only reason I can think of that we'd want to keep scalar_to_vector in this case is to help recognise the upper elts are undef but this doesn't seem to be a problem.

Differential Revision: https://reviews.llvm.org/D29097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293438 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-29 18:13:37 +00:00
Elena Demikhovsky
81518f1117 [X86 Codegen] Fixed a bug in unsigned saturation
PACKUSWB converts Signed word to Unsigned byte, (the same about DW) and it can't be used for umin+truncate pattern.
AVX-512 VPMOVUS* instructions fit the pattern since they convert Unsigned to Unsigned.

See https://llvm.org/bugs/show_bug.cgi?id=31773

Differential Revision: https://reviews.llvm.org/D29196



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293431 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-29 13:18:30 +00:00
Craig Topper
5cfd78fc85 [X86] Fix vector ANDN matching to work correctly when both inputs to the AND are XORs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293403 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-28 23:52:09 +00:00
Simon Pilgrim
10559c6633 [X86][SSE] Add support for combining ANDNP byte masks with target shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293178 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 14:31:12 +00:00
Simon Pilgrim
b81877488f [X86][SSE] Pull out target shuffle resolve code into helper. NFCI.
Pulled out code that removed unused inputs from a target shuffle mask into a helper function to allow it to be reused in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293175 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 13:06:02 +00:00
Craig Topper
facc9962a6 [AVX-512] Move the combine that runs combineBitcastForMaskedOp to the last DAG combine phase where I had originally meant to put it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293157 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 07:17:58 +00:00
Craig Topper
3cd2419e8b [X86] When bitcasting INSERT_SUBVECTOR/EXTRACT_SUBVECTOR to match masked operations, use the correct type for the immediate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293156 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-26 07:17:53 +00:00
Martin Bohme
a441aef21c [X86][SSE] Add explicit braces to avoid -Wdangling-else warning.
Reviewers: RKSimon

Subscribers: llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D29076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292924 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 12:31:30 +00:00
Simon Pilgrim
930bc2d28b Fix unused variable warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292921 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 11:54:27 +00:00
Simon Pilgrim
b9c01fbcf7 [X86][SSE] Add support for constant folding vector arithmetic shift by immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292919 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 11:46:13 +00:00
Simon Pilgrim
9334970101 [X86][SSE] Add support for constant folding vector logical shift by immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292915 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 11:21:57 +00:00
Craig Topper
f2b977986b [X86] Remove unnecessary peakThroughBitcasts call that's already take care of by the ISD::isBuildVectorAllOnes check below.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292894 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 06:57:29 +00:00
Craig Topper
a461826967 [X86] Don't split v8i32 all ones values if only AVX1 is available. Keep it intact and split it at isel.
This allows us to remove the check in ANDN combining that had to look through the extraction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292881 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 04:33:03 +00:00
Craig Topper
c144a2489f [X86] Remove Undef handling from extractSubVector. This is now handled inside getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292877 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 02:43:54 +00:00
Simon Pilgrim
f9440ffb06 [X86][SSE] Add missing X86ISD::ANDNP combines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292767 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-22 22:45:23 +00:00
Simon Pilgrim
160800e73a [X86][SSE] Improve shuffle combining with zero insertions
Add support for handling shuffles with scalar_to_vector(0)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292766 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-22 22:21:44 +00:00
Sanjay Patel
873d460b05 [x86] avoid crashing with illegal vector type (PR31672)
https://llvm.org/bugs/show_bug.cgi?id=31672


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292758 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-22 17:06:12 +00:00
Craig Topper
932a081385 [X86] Don't allow commuting to form phsub operations.
Fixes PR31714.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292713 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-21 06:59:38 +00:00
Simon Pilgrim
38e046e872 [X86][SSE] Improve comments describing combineTruncatedArithmetic. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292502 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 18:18:32 +00:00
Simon Pilgrim
2d628eed7f [X86][SSE] Attempt to pre-truncate arithmetic operations that have already been extended
As discussed on D28219 - it is profitable to combine trunc(binop (s/zext(x), s/zext(y)) to binop(trunc(s/zext(x)), trunc(s/zext(y))) assuming the trunc(ext()) will simplify further

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292493 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19 16:25:02 +00:00