6 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
490469a98c [TableGen] Ensure proper ordering of subtarget feature names
Recommit r297039 without the testcase. The MIR testcase did not work
well with MC code emitter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297080 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-06 21:26:49 +00:00
Krzysztof Parzyszek
628a420ef1 Revert r297039, it's causing some mysterious buildbot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297062 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-06 20:24:21 +00:00
Krzysztof Parzyszek
b69b5c5449 [TableGen] Ensure proper ordering of subtarget feature names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297039 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-06 18:08:37 +00:00
Matthias Braun
d6da5dbf7b Use print() instead of dump() in code
The dump() functions are meant to be used in a debugger, code should
typically use something like print(errs());

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293365 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-28 02:47:46 +00:00
Daniel Sanders
b313c742da Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.
Summary:
* ARM is omitted from this patch because this check appears to expose bugs in this target.
* Mips is omitted from this patch because this check either detects bugs or deliberate
  emission of instructions that don't satisfy their predicates. One deliberate
  use is the SYNC instruction where the version with an operand is correctly
  defined as requiring MIPS32 while the version without an operand is defined
  as an alias of 'SYNC 0' and requires MIPS2.
* X86 is omitted from this patch because it doesn't use the tablegen-erated
  MCCodeEmitter infrastructure.

Patches for ARM and Mips will follow.

Depends on D25617

Reviewers: tstellarAMD, jmolloy

Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits

Differential Revision: https://reviews.llvm.org/D25618

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287439 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-19 13:05:44 +00:00
Daniel Sanders
57a599ec1a [tablegen] Extract portions of AsmMatcherEmitter for re-use by another generator. NFC.
Summary:
This change is preparation for a change that will allow targets to verify that the instructions
they emit meet the predicates they specify. This is useful to ensure that C++
legalization/lowering/instruction-selection doesn't incorrectly select code for a different
subtarget than intended. Such cases are not caught by the integrated assembler when emitting
instructions directly to an object file.

Reviewers: qcolombet

Subscribers: qcolombet, beanz, mgorny, llvm-commits, modocache

Differential Revision: https://reviews.llvm.org/D25614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286945 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-15 09:51:02 +00:00