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3353 Commits

Author SHA1 Message Date
NAKAMURA Takumi
3328a1dadc TableGen/X86RecognizableInstr.h: Prune out-of-date "@param isSSE". [-Wdocumentation] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200628 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-02 10:53:36 +00:00
Craig Topper
6b6dfa5c5a Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-02 09:25:09 +00:00
Craig Topper
3c53b6f1ec Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200625 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-02 07:46:05 +00:00
Craig Topper
1415ca1781 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200624 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-02 07:08:01 +00:00
Craig Topper
f0b161d774 Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200522 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 08:47:06 +00:00
Craig Topper
45b8e5fa49 Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200520 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 07:00:55 +00:00
Craig Topper
28d965d300 Couple minor formatting fixes to the XXXGenDAGISel.inc files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200459 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-30 06:42:52 +00:00
Craig Topper
01a5c17219 Delete the Matchers stored in the SmallVectors in SwitchOpcodeMatcher/SwitchTypeMatcher. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200377 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-29 07:06:07 +00:00
David Woodhouse
4faa861f19 Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200349 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-28 23:13:18 +00:00
David Woodhouse
4396f5d9d2 Change MCStreamer EmitInstruction interface to take subtarget info 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200345 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-28 23:12:42 +00:00
Craig Topper
90790c3217 Improve handling of EnforceSmallerThan. Remove all types that are smaller from the larger set not just the smallest type from the smaller set. Ensure 'smaller' vectors have the same or fewer total bits. Similar for 'larger' vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200287 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-28 04:49:01 +00:00
Craig Topper
55604d9716 Don't use EnforceSmallerThan for EnforceVectorSubVectorTypeIs. EnforceSmallerThan doesn't handle vectors quite right and should really enforce that vectors have the same number of elements. Add explicit checks for vector element count differing in EnforceVectorSubVectorTypeIs instead. This removes some unnecessary type checks in X86GenDAGISel.inc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200091 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-25 17:40:33 +00:00
Craig Topper
858594edb0 Fix typo in commment tyep->type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200089 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-25 17:34:23 +00:00
Craig Topper
f6deb18968 Use isConcrete and getConcrete instead of using TypeVec directly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200071 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-25 05:33:48 +00:00
Craig Topper
f5f44a149e Fix EnforceSmallerThan to check !hasVectorTypes on the other type instead of this type to force this type to be scalar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200070 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-25 05:17:38 +00:00
Craig Topper
82f50dc0c2 Remove TGValueTypes.cpp from CMakeLists.txt which I forgot to do in r200036. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200037 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-24 20:51:32 +00:00
Craig Topper
f3474549ba Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200036 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-24 20:50:47 +00:00
Alp Toker
ae43cab6ba Fix known typos 
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-24 17:20:08 +00:00
David Woodhouse
674140fc3e ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199806 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 15:08:36 +00:00
David Woodhouse
ccbfd5b18a [x86] Allow address-size overrides for STOS[BWLQ] (PR9385) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199804 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 15:08:21 +00:00
David Woodhouse
db9fa461d7 [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199803 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 15:08:08 +00:00
Craig Topper
8f74ea3fa1 Use ArrayRef to simplify some code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199712 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-21 07:20:05 +00:00
David Woodhouse
9334b07527 [x86] Fix disassembly of MOV16ao16 et al. 
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199654 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 12:02:53 +00:00
Craig Topper
85026d9375 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-16 07:36:58 +00:00
Kostya Serebryany
3846ce9490 replace LeakSanitizerIsTurnedOffForTheCurrentProcess with __lsan_is_turned_off, but this time hide it under __has_feature(address_sanitizer); also include <sanitizer/lsan_interface.h> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199303 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-15 07:59:37 +00:00
Craig Topper
38e6f7301d Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199295 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-15 05:02:02 +00:00
Lang Hames
5f33cbc414 Add FPExt option to CCValAssign::LocInfo. When generating calling-convention 
promotion code, Tablegen will now select FPExt for floating point promotions
(previously it had returned AExt, which is not valid for floating point types).

Any out-of-tree targets that were relying on AExt being returned for FP
promotions will need to update their code check for FPExt instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199252 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 19:56:36 +00:00
Craig Topper
8e31bc35ec Remove stray comma in enum to satisfy -Wpedantic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199194 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 08:07:10 +00:00
Craig Topper
525ae45240 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-14 07:41:20 +00:00
Elena Demikhovsky
1f044d443d AVX-512: Embedded Rounding Control - encoding and printing 
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-13 12:55:03 +00:00
Roman Divacky
af43b47c5a Constant propagate MachineInstrClassName. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198969 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-10 22:59:49 +00:00
Rafael Espindola
dd86e54b61 All backends use MC now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198959 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-10 21:49:27 +00:00
Kostya Serebryany
ab39685c77 reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198922 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-10 08:05:42 +00:00
Alp Toker
d92ff21d6f Revert "Disable LeakSanitizer in TableGen binaries, see PR18325" 
To declare or define reserved identifers is undefined behaviour in standard
C++. This needs to be addressed in compiler-rt before it can be used in LLVM.

See the list discussion for details.

This reverts commit r198858.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198884 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-09 19:40:55 +00:00
Kostya Serebryany
c50299bab6 Disable LeakSanitizer in TableGen binaries, see PR18325 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198858 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-09 09:26:26 +00:00
David Woodhouse
aab59870a4 [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand 
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 12:58:24 +00:00
Craig Topper
c8fd2c57c8 The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198589 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-06 06:57:27 +00:00
Craig Topper
adb7d3b49b Use patterns to remove some duplicate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198550 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 06:55:48 +00:00
Craig Topper
6a69266fed Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198547 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 05:46:38 +00:00
Craig Topper
09104ff9df Remove no longer needed x86 disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198546 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 05:10:07 +00:00
Craig Topper
01cb7fa977 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198545 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:55:55 +00:00
Craig Topper
2b5dc93948 Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198544 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:32:42 +00:00
Craig Topper
527f132627 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:17:28 +00:00
Craig Topper
e43a0f8015 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198530 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 01:35:51 +00:00
Craig Topper
62fe07a1ac Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198529 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 01:34:12 +00:00
Craig Topper
29d56f68c6 Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198515 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-04 22:29:41 +00:00
Craig Topper
030ceadd69 Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198475 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-04 05:09:27 +00:00
Hal Finkel
6fa9961327 [TableGen] Handle ValueType in CodeGenDAGPatterns GetNumNodeResults 
A ValueType in a pattern dag is a type cast, and GetNumNodeResults should
handle it (the type cast has only one result).

This comes up, for example, during the type checking of pattern fragments, for
example, AArch64's Neon_combine_2d fragment is:
  dag Operands = (ops node:$Rm, node:$Rn);
  dag Fragment = (v2f64 (concat_vectors (v1f64 node:$Rm), (v1f64 node:$Rn)));

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198347 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 20:47:05 +00:00
Craig Topper
d573aba8e1 Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198336 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 19:12:10 +00:00
Craig Topper
163868fec5 Remove unused HasFROperands field from disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198332 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 18:44:21 +00:00