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71 Commits

Author SHA1 Message Date
Matt Arsenault 65181f7b75 AMDGPU/GlobalISel: Cleanup constant legality 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327774 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-17 15:17:48 +00:00
Matt Arsenault 417485b734 AMDGPU/GlobalISel: Basic G_GEP legality 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327773 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-17 15:17:45 +00:00
Matt Arsenault 177d1142dd AMDGPU/GlobalISel: Basic legality for load/store 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327772 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-17 15:17:41 +00:00
Matt Arsenault 7f9dbc4419 AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327269 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-12 13:35:53 +00:00
Matt Arsenault e0eff38b22 AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUES 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327268 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-12 13:35:49 +00:00
Matt Arsenault b3834e5d6b AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327267 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-12 13:35:43 +00:00
Matt Arsenault f246669c10 AMDGPU/GlobalISel: Add InstrMapping for G_EXTRACT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326715 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-05 16:25:18 +00:00
Matt Arsenault 4e77263fcb AMDGPU/GlobalISel: Make some G_EXTRACTs legal 
As far as I can tell legalization of weird sizes for the
output type isn't implemented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326714 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-05 16:25:15 +00:00
Matt Arsenault 73675f1a18 AMDGPU/GlobalISel: InstrMapping for G_ZEXT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326589 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 16:55:37 +00:00
Matt Arsenault 4f133997d7 AMDGPU/GlobalISel: InstrMapping for G_TRUNC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326588 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 16:55:33 +00:00
Matt Arsenault 8030f1eaa3 AMDGPU/GlobalISel: Define InstrMappings for G_FCMP 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326587 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 16:53:15 +00:00
Matt Arsenault 78bc395115 AMDGPU/GlobalISel: Define instruction mapping for @llvm.minnum 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326586 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 16:40:17 +00:00
Matt Arsenault de514539f2 AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnum 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326567 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 12:23:00 +00:00
Matt Arsenault 0e5b4bc59c AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSI 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326534 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 02:19:16 +00:00
Matt Arsenault 3ec91dfb66 AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUI 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326533 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 02:19:11 +00:00
Matt Arsenault f3dbef61bd AMDGPU/GlobalISel: Define instruction mapping for G_FMUL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326532 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 02:17:01 +00:00
Matt Arsenault 6f9952dce3 AMDGPU/GlobalISel: Define instruction mapping for G_FADD 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326526 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 01:22:13 +00:00
Matt Arsenault 52088d0a5f AMDGPU/GlobalISel: Define instruction mapping for G_SHL 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326525 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 01:22:10 +00:00
Matt Arsenault 95f12ebe5c AMDGPU/GlobalISel: Define instruction mapping for G_XOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326524 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 01:22:06 +00:00
Matt Arsenault 8f583a24ce AMDGPU/GlobalISel: Define instruction mapping for G_AND 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326523 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-02 01:22:01 +00:00
Matt Arsenault 05580dd9e5 AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtz 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326490 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 21:25:30 +00:00
Matt Arsenault 9fcecef726 AMDGPU/GlobalISel: Define instruction mapping for G_OR 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326489 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 21:25:25 +00:00
Matt Arsenault e9e42e8917 AMDGPU/GlobalISel: Define instruction mapping for G_BITCAST 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326482 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 20:59:44 +00:00
Matt Arsenault df1563c176 AMDGPU/GlobalISel: Mark i32->i64 zext as legal 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326481 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 20:56:21 +00:00
Matt Arsenault e82f69197b AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326479 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 20:40:55 +00:00
Matt Arsenault bc5e95e9a9 AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.exp 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326477 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 20:24:37 +00:00
Matt Arsenault 92b4d60ae0 AMDGPU/GlobalISel: Define InstrMappings for G_ICMP 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326472 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 19:27:10 +00:00
Matt Arsenault 78411cf894 AMDGPU/GlobalISel: Make i32 mul legal 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326471 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 19:22:05 +00:00
Matt Arsenault 435d0a8937 AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326470 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 19:16:52 +00:00
Matt Arsenault e4d2cea91d AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANT 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326468 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 19:13:30 +00:00
Matt Arsenault 5b58d668a1 AMDGPU/GlobalISel: Make i32 xor legal 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326466 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 19:09:21 +00:00
Matt Arsenault 7537e26848 AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legal 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326465 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 19:09:16 +00:00
Matt Arsenault 41f826cda5 AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legal 
Patch by Tom Stellard

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326464 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-03-01 19:04:25 +00:00
Matt Arsenault ca0bccecf5 AMDGPU/GlobalISel: Make f64 constants legal 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326101 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-02-26 17:20:43 +00:00
Yaxun Liu 2930e5c52d [AMDGPU] Change constant addr space to 4 
Differential Revision: https://reviews.llvm.org/D43170


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325030 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-02-13 18:00:25 +00:00
Tom Stellard d595719b5e AMDGPU/GlobalISel: Mark 32-bit G_FPTOUI as legal 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D42152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324446 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-02-07 04:47:59 +00:00
Puyan Lotfi 1076969bfe Followup on Proposal to move MIR physical register namespace to '$' sigil. 
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323922 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-01-31 22:04:26 +00:00
Aditya Nandakumar 0053d0421c [GISel]: Rework legalization algorithm for better elimination of 
artifacts along with DCE

Legalization Artifacts are all those insts that are there to make the
type system happy. Currently, the target needs to say all combinations
of extends and truncs are legal and there's no way of verifying that
post legalization, we only have *truly* legal instructions. This patch
changes roughly the legalization algorithm to process all illegal insts
at one go, and then process all truncs/extends that were added to
satisfy the type constraints separately trying to combine trivial cases
until they converge. This has the added benefit that, the target
legalizerinfo can only say which truncs and extends are okay and the
artifact combiner would combine away other exts and truncs.

Updated legalization algorithm to roughly the following pseudo code.

WorkList Insts, Artifacts;
collect_all_insts_and_artifacts(Insts, Artifacts);

do {
  for (Inst in Insts)
         legalizeInstrStep(Inst, Insts, Artifacts);
  for (Artifact in Artifacts)
         tryCombineArtifact(Artifact, Insts, Artifacts);
} while(!Insts.empty());

Also, wrote a simple wrapper equivalent to SetVector, except for
erasing, it avoids moving all elements over by one and instead just
nulls them out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318210 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-11-14 22:42:19 +00:00
Bjorn Pettersson 4cbab70b62 [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 
Summary:
Print %subreg.<subregidxname> instead of just the subregister
index when printing immediate operands corresponding to subreg
indices in INSERT_SUBREG, EXTRACT_SUBREG, SUBREG_TO_REG and
REG_SEQUENCE.

Reviewers: qcolombet, MatzeB

Reviewed By: MatzeB

Subscribers: nhaehnle, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D39696

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317513 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-11-06 21:46:06 +00:00
Tom Stellard f94e4f3ed7 AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D38439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316815 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-27 23:57:41 +00:00
Justin Bogner edab757966 MIR: Print the register class or bank in vreg defs 
This updates the MIRPrinter to include the regclass when printing
virtual register defs, which is already valid syntax for the
parser. That is, given 64 bit %0 and %1 in a "gpr" regbank,

  %1(s64) = COPY %0(s64)

would now be written as

  %1:gpr(s64) = COPY %0(s64)

While this change alone introduces a bit of redundancy with the
registers block, it allows us to update the tests to be more concise
and understandable and brings us closer to being able to remove the
registers block completely.

Note: We generally only print the class in defs, but there is one
exception. If there are uses without any defs whatsoever, we'll print
the class on all uses. I'm not completely convinced this comes up in
meaningful machine IR, but for now the MIRParser and MachineVerifier
both accept that kind of stuff, so we don't want to have a situation
where we can print something we can't parse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316479 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-24 18:04:54 +00:00
Justin Bogner ba2fa173d9 Canonicalize a large number of mir tests using update_mir_test_checks 
This converts a large and somewhat arbitrary set of tests to use
update_mir_test_checks. I ran the script on all of the tests I expect
to need to modify for an upcoming mir syntax change and kept the ones
that obviously didn't change the tests in ways that might make it
harder to understand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316137 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-10-18 23:18:12 +00:00
Matt Arsenault e525b474ef AMDGPU: Remove -mcpu=SI 
Leftover from before amdgcn/r600 split.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310277 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-07 18:30:35 +00:00
Tom Stellard 58dd3a3775 AMDGPU/GlobalISel: Mark 32-bit G_FMUL as legal 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D36218

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309898 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-02 22:56:30 +00:00
Tom Stellard c0ce68eb67 AMDGPU/GlobalISel: Add support for amdgpu_vs calling convention 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D35916

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309675 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-08-01 12:38:33 +00:00
Tom Stellard 9f8f952c9a AMDGPU/GlobalISel: Mark 32-bit G_OR as legal 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D35127

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309165 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-07-26 20:00:53 +00:00
Tom Stellard 8d3ca7cfeb AMDGPU/GlobalISel: Mark 32-bit G_SHL as legal 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D34589

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306298 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-26 15:56:52 +00:00
Tom Stellard 111d1b387d AMDGPU/GlobalISel: Mark 32-bit G_AND as legal 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D34349

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306112 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-23 15:17:17 +00:00
Tom Stellard 865802ce11 AMDGPU/GlobalISel: Mark G_BITCAST s32 <--> <2 x s16> legal 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D34129

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305692 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-19 13:15:45 +00:00
Tom Stellard c746f23920 AMDGPU/GlobalISel: Mark 32-bit G_ADD as legal 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D33992

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305232 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-06-12 20:54:56 +00:00