Summary:
- Give it a shorter name (because we're going to refer to it often from
SelectionDAG and friends).
- Split the flags and alignment into separate variables.
- Specialize FlagsEnumTraits for it, so we can do bitwise ops on it
without losing type information.
- Make some enum values constants in MachineMemOperand instead.
MOMaxBits should not be a valid Flag.
- Simplify some of the bitwise ops for dealing with Flags.
Reviewers: chandlerc
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D22281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275438 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
In this patch we implement the following parts of XRay:
- Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches.
- Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts).
- X86-specific nop sleds as described in the white paper.
- A machine function pass that adds the different instrumentation marker instructions at a very late stage.
- A way of identifying which return opcode is considered "normal" for each architecture.
There are some caveats here:
1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet.
2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library.
Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk
Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits
Differential Revision: http://reviews.llvm.org/D19904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275367 91177308-0d34-0410-b5e6-96231b3b80d8
While some code paths in MIRParserImpl::parse() already returned nullptr
in case of error one of the important ones did not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275355 91177308-0d34-0410-b5e6-96231b3b80d8
Avoid exposing a cl::opt in a public header and instead promote this
option in the API.
Alternatively, we could land the cl::opt in CommandFlags.h so that
it is available to every tool, but we would still have to find an
option for clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275348 91177308-0d34-0410-b5e6-96231b3b80d8
IPRA try to optimize caller saved register by propagating register
usage information from callee to caller so it is beneficial to have
caller saved registers compare to callee saved registers when IPRA
is enabled. Please find more detailed explanation here
https://groups.google.com/d/msg/llvm-dev/XRzGhJ9wtZg/tjAJqb0eEgAJ.
This change makes local function do not have any callee preserved
register when IPRA is enabled. A simple test case is also added to
verify this change.
Patch by Vivek Pandya <vivekvpandya@gmail.com>
Differential Revision: http://reviews.llvm.org/D21561
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275347 91177308-0d34-0410-b5e6-96231b3b80d8
Code cleanup: Move references to SlotMapping and SourceMgr into the
PerFunctionMIParsingState to avoid unnecessary passing around in
parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275342 91177308-0d34-0410-b5e6-96231b3b80d8
If a masked loads is not added to the chain, it should not reset the chain's
root.
This fixes the remaining part of PR28515.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275340 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
Previously it would say we had an invariant load if any of the memory
operands were invariant. But the load should be invariant only if *all*
the memory operands are invariant.
No testcase because this has proven to be very difficult to tickle in
practice. As just one example, ARM's ldrd instruction, which loads 64
bits into two 32-bit regs, is theoretically affected by this. But when
it's produced, it loses its memoperands' invariance bits!
Reviewers: jfb
Subscribers: llvm-commits, aemerson
Differential Revision: http://reviews.llvm.org/D22318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275331 91177308-0d34-0410-b5e6-96231b3b80d8
Code cleanup: The PerFunctionMIParsingState is per function, moving a
reference into PFS we can avoid passing around the MachineFunction in an
extra parameter most of the time.
Also change most signatures to consistently pass PFS reference first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275329 91177308-0d34-0410-b5e6-96231b3b80d8
Currently the MIR framework prints all its outputs (errors and actual
representation) on stderr.
This patch fixes that by printing the regular output in the output
specified with -o.
Differential Revision: http://reviews.llvm.org/D22251
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275314 91177308-0d34-0410-b5e6-96231b3b80d8
We can freeze the registers after the MachineFrameInfo has been configured (by
telling it about calls, inline asm, ...). This doesn't happen at all yet, but
will be part of IR translation.
Fixes -verify-machineinstrs assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275221 91177308-0d34-0410-b5e6-96231b3b80d8
Use LivePhysRegs with a backwards walking algorithm to update live in
lists, this way the results do not depend on the presence of kill flags
anymore.
This patch also reduces the number of registers added as live-in.
Previously all pristine registers as well as all sub registers of a
super register were added resulting in unnecessarily large live in
lists. This fixed https://llvm.org/PR25263.
Differential Revision: http://reviews.llvm.org/D22027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275201 91177308-0d34-0410-b5e6-96231b3b80d8
Added support for:
1. Multi dimension array.
2. Array of structure type, which previously was declared incompletely.
3. Dynamic size array.
4. Array where element type is a typedef, volatile or constant (this should resolve PR28311).
Differential Revision: http://reviews.llvm.org/D21526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275167 91177308-0d34-0410-b5e6-96231b3b80d8
Blocks to be tail-merged may share more than one successor. Correct the
comment to state that they share a specific successor, SuccBB, rather
than a single successor, which is not true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275104 91177308-0d34-0410-b5e6-96231b3b80d8
Preserve assembly comments from input in output assembly and flags to
toggle property. This is on by default for inline assembly and off in
llvm-mc.
Parsed comments are emitted immediately before an EOL which generally
places them on the expected line.
Reviewers: rtrieu, dwmw2, rnk, majnemer
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D20020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275058 91177308-0d34-0410-b5e6-96231b3b80d8
There exists no relocation which can describe the address of a
dllimported variable: do not try to describe their location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274986 91177308-0d34-0410-b5e6-96231b3b80d8
Drive-by improvement: We would 1) add CSRs, 2) remove callee saved CSRs
and 3) add all CSRs again for the return block. Just adding CSRs once
obviously gives the same results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274955 91177308-0d34-0410-b5e6-96231b3b80d8
An identity COPY like this:
%AL = COPY %AL, %EAX<imp-def>
has no semantic effect, but encodes liveness information: Further users
of %EAX only depend on this instruction even though it does not define
the full register.
Replace the COPY with a KILL instruction in those cases to maintain this
liveness information. (This reverts a small part of r238588 but this
time adds a comment explaining why a KILL instruction is useful).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274952 91177308-0d34-0410-b5e6-96231b3b80d8
Because isReallyTriviallyReMaterializableGeneric puts many limits on
rematerializable instructions, this fix can prevent instructions with
tied virtual operands and instructions with virtual register uses from
being kept in DeadRemat, so as to workaround the live interval consistency
problem for the dummy instructions kept in DeadRemat.
But we still need to fix the live interval consistency problem. This patch
is just a short time relieve. PR28464 has been filed as a reminder.
Differential Revision: http://reviews.llvm.org/D19486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274928 91177308-0d34-0410-b5e6-96231b3b80d8
Mostly through preferring MachineInstr&, avoid implicit conversions from
iterator to pointer.
Although this may bitrot (since there are other uses blocking me from
removing the implicit operator), this removes the last of the implicit
conversions from MachineInstrBundleIterator to MachineInstr* in the
LLVMCodeGen build target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274893 91177308-0d34-0410-b5e6-96231b3b80d8
Prefer MachineInstr& in order to avoid implicit conversions from
MachineInstrBundleIterator to MachineInstr*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274888 91177308-0d34-0410-b5e6-96231b3b80d8
The createRegAllocPass reads and writes to a global variable 'Registry'
via calls to getDefault and setDefault. Run this under a call_once to
avoid races.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274875 91177308-0d34-0410-b5e6-96231b3b80d8
Justin Lebar